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[78.44.132.10]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-48c71d2d563sm3896568f8f.41.2026.10.07.00.46.32 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 00:46:33 -0700 (PDT) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Wed, 07 Oct 2026 09:46:31 +0200 Message-Id: Subject: Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available Cc: , , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" , "Samuel Holland" , "Andy Chiu" , "Guodong Xu" , "Zong Li" To: "Charlie Jenkins" From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20261006075303.205216-1-radim.krcmar@oss.qualcomm.com> <20261006075303.205216-2-radim.krcmar@oss.qualcomm.com> <179133089395.137225.157195939155119911.b4-review@b4> In-Reply-To: <179133089395.137225.157195939155119911.b4-review@b4> X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDAzMCBTYWx0ZWRfXxJ1nv4Nd3/en /J9Rkrb4dK7kVbysO+lFKKu2shrKHafZMB07YMZ9yW1aRXrX0kqVTSmwmEX3cH8j7KIJcXeC++I YBIFkuv/KdlAoYHGjAnUCiRc5ncMfjo= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDAzMCBTYWx0ZWRfX+VDd7WpZ8wd5 LnC57szrdaLMqWfEbJMUunI7jTt3/BDhuC2vnjDXbZWd7Wf+yNe2cG7FRuAGPcJa8lbPmw71iGq 54QPLlbx5JS8wFnjhYd2JG/b7MPO6JTsODJJ135PeaI/Dr6TuwAGOIxtjCtmJQwupVhjhgPHSxI G7KojaEHfAJme9P8zoQWa79DPDROzSUQFh99uDjzPPhd4NbF80n5y8VxIbG0KRmgDo50+vLqOKq Qi3j6Jn25W/h2yrVXgWh6dPxt0BfwhQM4Jmlz5mBaBYZ6P8q8tCbuL4GwABI9rcD8IpxGeNjCIb OAUsijKfMJGR4q3BNleLudckEbllf9EvfkHVDZYWhRTXW8yK15a0SkyqHMC6ZkZPXCG4TB7YQY8 IoLXTO8fT0XpiVpewtAcSrKUSjE0ss4FBPCeyNan9LGMi91uDNo9RZFVKLuH4cTP7MS/mbUJqdf zbGrwjunn6eT3hv1eDA== X-Proofpoint-GUID: yCWwNlWQOGHrFyPYNcnS7WD6MY-mAgoO X-Proofpoint-ORIG-GUID: yCWwNlWQOGHrFyPYNcnS7WD6MY-mAgoO X-Authority-Analysis: v=2.4 cv=LvYHWXdc c=1 sm=1 tr=0 ts=6ac5f8db cx=c_pps a=50t2pK5VMbmlHzFWWp8p/g==:117 a=kVq+qqu7synz0czdOrlqmQ==:17 a=IkcTkHD0fZMA:10 a=660iZSQnnn4A:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=eoimf2acIAo5FJnRuUoq:22 a=pGLkceISAAAA:8 a=EUspDBNiAAAA:8 a=_j74ZTOZETwGzg2yP1kA:9 a=QEXdDO2ut3YA:10 a=IoWCM6iH3mJn3m4BftBB:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_03,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 spamscore=0 impostorscore=0 suspectscore=0 lowpriorityscore=0 clxscore=1015 bulkscore=0 adultscore=0 phishscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070030 2026-10-06T16:54:53-07:00, Charlie Jenkins : >> User-mode use of Zcd, Zcf, Zfa, Zfbfmin, Zfh and Zfhmin requires >> non-Off sstatus.FS, which we set only when has_fpu() (CONFIG_FPU and D >> on all harts). The vector floating-point extensions Zve32f, Zve64f, >> Zve64d, Zvfbfmin, Zvfbfwma, Zvfh and Zvfhmin require it as well, but >> hwprobe gates them only on has_vector(). hwprobe otherwise reports the >> extensions from the per-hart ISA bitmaps alone, so it can advertise >> extensions that are always disabled in user-mode. >>=20 >> Report correct environment to user-mode. >>=20 >> Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and= zfhmin") >> Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into = hwprobe interface") >> Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions") >> Signed-off-by: Radim Kr=C4=8Dm=C3=A1=C5=99 >> >> diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwp= robe.c >> index 7818e1d32622..b57ccd116bb1 100644 >> --- a/arch/riscv/kernel/sys_hwprobe.c >> +++ b/arch/riscv/kernel/sys_hwprobe.c >> @@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *= pair, >> if (has_vector()) { >> EXT_KEY(isainfo->isa, ZVBB, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVBC, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVFH, pair->value, missing); >> - EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVKB, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVKG, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing); >> @@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe = *pair, >> EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing); >> EXT_KEY(isainfo->isa, ZVKT, pair->value, missing); >> + >> + if (has_fpu()) { >> + EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVFH, pair->value, missing); >> + EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing); > > The vector Kconfig is gated on FPU=3Dy so the vector instructions can't > ever be enabled when FPU=3Dn. Right, I'll make the commit message clearer in v2. (Zve32x and hence has_vector() can technically exist without CONFIG_FPU, so future implementations might require use to remove the dependency.) I think this check is adding a bit of sanity, although the platforms where it comes into play are already very wild. has_fpu()=3Dfalse and has_vector()=3Dtrue is possible on heterogenous platforms since the filtering/validation of floating vector extensions happens on F extension support on that hart alone. If other hart doesn't support F, all harts will trap floating vector extension as mstatus.FS=3DOff, although scalar vector should still work because has_vector() isn't keyed on V support, but only on Zve32x. Thanks.