From: "Alexandre Courbot" <acourbot@nvidia.com>
To: "Antonin Malzieu Ridolfi via B4 Relay"
<devnull+dev.nanonej.com@kernel.org>
Cc: <dev@nanonej.com>, "Danilo Krummrich" <dakr@kernel.org>,
"Alice Ryhl" <aliceryhl@google.com>,
"David Airlie" <airlied@gmail.com>,
"Simona Vetter" <simona@ffwll.ch>, <linux-kernel@vger.kernel.org>,
<nova-gpu@lists.linux.dev>, <dri-devel@lists.freedesktop.org>
Subject: Re: [PATCH v3 2/4] gpu: nova-core: falcon: Extract PRISCV register
Date: Thu, 08 Oct 2026 22:41:55 +0900 [thread overview]
Message-ID: <DLZI0RL58KFW.3TV88Q5GZV5M2@nvidia.com> (raw)
In-Reply-To: <20260923-b4-extract-pfsp-registers-to-falcon-mod-v3-2-cd26aa94c021@nanonej.com>
On Wed Sep 23, 2026 at 10:09 AM JST, Antonin Malzieu Ridolfi via B4 Relay wrote:
<...>
> -// PFALCON registers are defined in the root `regs.rs` but are part of the falcon
> -// interface, accessed by the whole falcon module. They are re-exported here so
> -// falcon code can use a single `regs::` prefix.
> -// Once the PFALCON family moves out of the root module, these re-exports become
> +// PFALCON, PFALCON2 and FUSE registers are defined in the root `regs.rs` but
> +// are part of the falcon interface, accessed by the whole falcon module. They
> +// are re-exported here so falcon code can use a single `regs::` prefix.
> +// Once these families move out of the root module, these re-exports become
> // plain definitions.
> pub(super) use crate::regs::{
> - NV_PFALCON_FALCON_BOOTVEC, NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS,
> - NV_PFALCON_FALCON_DMACTL, NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1,
> - NV_PFALCON_FALCON_DMATRFCMD, NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS,
> - NV_PFALCON_FALCON_DMEMC, NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC,
> - NV_PFALCON_FALCON_EMEMD, NV_PFALCON_FALCON_IMEMC, NV_PFALCON_FALCON_IMEMD,
> - NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0, NV_PFALCON_FALCON_MAILBOX1,
> - NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL, NV_PFALCON_FBIF_TRANSCFG,
> + NV_FUSE_OPT_FPF_GSP_UCODE1_VERSION, NV_FUSE_OPT_FPF_NVDEC_UCODE1_VERSION,
> + NV_FUSE_OPT_FPF_SEC2_UCODE1_VERSION, NV_FUSE_OPT_FPF_SIZE,
> + NV_PFALCON2_FALCON_BROM_CURR_UCODE_ID, NV_PFALCON2_FALCON_BROM_ENGIDMASK,
> + NV_PFALCON2_FALCON_BROM_PARAADDR, NV_PFALCON2_FALCON_MOD_SEL, NV_PFALCON_FALCON_BOOTVEC,
> + NV_PFALCON_FALCON_CPUCTL, NV_PFALCON_FALCON_CPUCTL_ALIAS, NV_PFALCON_FALCON_DMACTL,
> + NV_PFALCON_FALCON_DMATRFBASE, NV_PFALCON_FALCON_DMATRFBASE1, NV_PFALCON_FALCON_DMATRFCMD,
> + NV_PFALCON_FALCON_DMATRFFBOFFS, NV_PFALCON_FALCON_DMATRFMOFFS, NV_PFALCON_FALCON_DMEMC,
> + NV_PFALCON_FALCON_DMEMD, NV_PFALCON_FALCON_EMEMC, NV_PFALCON_FALCON_EMEMD,
> + NV_PFALCON_FALCON_ENGINE, NV_PFALCON_FALCON_HWCFG2, NV_PFALCON_FALCON_IMEMC,
> + NV_PFALCON_FALCON_IMEMD, NV_PFALCON_FALCON_IMEMT, NV_PFALCON_FALCON_MAILBOX0,
> + NV_PFALCON_FALCON_MAILBOX1, NV_PFALCON_FALCON_OS, NV_PFALCON_FALCON_RM, NV_PFALCON_FBIF_CTL,
> + NV_PFALCON_FBIF_TRANSCFG,
Mmm, this is not great, quite a bit of churn and in the end we only need
to import 4 registers IIUC.
How about this: as a first patch, switch the registers module used by
all `falcon` submodules to the falcon-local one, which only does
`pub(super) use crate::regs::*;`
Then, move the registers as you are doing, but without updating the
imported list since it is largely exhaustive.
It is only after all the registers have been moved that you can import
the 4 we still need. Or rather, I'd suggest referencing these using
`crate::regs::` to clearly signal they do not belong here, and remove
the `use crate::regs::*` that the first patch added to `falcon/regs.rs`.
That way we limit the churn in the series, and end up with a nice, clean
state.
(my apologies as this will require a rebase - sorry also for the time it
took me to come back to this)
next prev parent reply other threads:[~2026-10-08 13:42 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-23 1:09 [PATCH v3 0/4] gpu: nova-core: Extract falcon registers Antonin Malzieu Ridolfi via B4 Relay
2026-09-23 1:09 ` [PATCH v3 1/4] gpu: nova-core: Extract PFSP register definitions Antonin Malzieu Ridolfi via B4 Relay
2026-09-23 1:09 ` [PATCH v3 2/4] gpu: nova-core: falcon: Extract PRISCV register Antonin Malzieu Ridolfi via B4 Relay
2026-10-08 13:41 ` Alexandre Courbot [this message]
2026-09-23 1:09 ` [PATCH v3 3/4] gpu: nova-core: falcon: Extract PFALCON2 register Antonin Malzieu Ridolfi via B4 Relay
2026-09-23 1:09 ` [PATCH v3 4/4] gpu: nova-core: Extract PFALCON register Antonin Malzieu Ridolfi via B4 Relay
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