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mx.google.com; dkim=pass header.i=@xilinx.onmicrosoft.com header.s=selector1-xilinx-com header.b=1a4l7g8y; spf=pass (google.com: domain of jollys@xilinx.com designates 104.47.33.57 as permitted sender) smtp.mailfrom=JOLLYS@xilinx.com Authentication-Results: mx.google.com; dkim=pass header.i=@xilinx.onmicrosoft.com header.s=selector1-xilinx-com header.b=1a4l7g8y; spf=pass (google.com: domain of jollys@xilinx.com designates 104.47.33.57 as permitted sender) smtp.mailfrom=JOLLYS@xilinx.com From: Jolly Shah To: Mark Rutland CC: "ard.biesheuvel@linaro.org" , "mingo@kernel.org" , "gregkh@linuxfoundation.org" , "matt@codeblueprint.co.uk" , "sudeep.holla@arm.com" , "hkallweit1@gmail.com" , "keescook@chromium.org" , "dmitry.torokhov@gmail.com" , "michal.simek@xilinx.com" , "robh+dt@kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" , "devicetree@vger.kernel.org" , Rajan Vaja Subject: RE: [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP firmware driver Thread-Topic: [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP firmware driver Thread-Index: AQHTlWou2XFDSgiaBEabjrwcvuQZWKOOVW8AgABxHPCAAJ7JgIAA3v1w Date: Thu, 1 Feb 2018 23:54:05 +0000 Message-ID: References: <1516836074-4149-1-git-send-email-jollys@xilinx.com> <1516836074-4149-3-git-send-email-jollys@xilinx.com> <20180131182012.oshjmvahetaizlbu@lakrids.cambridge.arm.com> <20180201103321.fftn37mgzbk6oltl@lakrids.cambridge.arm.com> In-Reply-To: <20180201103321.fftn37mgzbk6oltl@lakrids.cambridge.arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: x-originating-ip: [149.199.62.254] x-ms-publictraffictype: Email x-microsoft-exchange-diagnostics: 1;DM2PR0201MB1040;7:t65Ckh3ZwT29XjlbqzCPU4RmYRLGoziVViKJjI9tPKkm8lqesZVZzxKLwb3QfnlykWfRq1RUy7Kty5VFTpSBdiZLR7hSA/O9d03Q6F8xDndeCi1fE7RdMVk9zUferMVP+QG/RZSMBQ6Q90is639Wlw4QRkoqRRaaTWnSgJkGWEKwInp2DjILHNethc8mG6yqvdzyltJRqHVuVYxbsf2MDFmBHDURqOZCGNjswQfG921F3lg/iOCI33Hz/47Iz9TX x-ms-exchange-antispam-srfa-diagnostics: SSOS;SSOR; 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x-ms-traffictypediagnostic: DM2PR0201MB1040: authentication-results: spf=none (sender IP is ) smtp.mailfrom=JOLLYS@xilinx.com; x-microsoft-antispam-prvs: x-exchange-antispam-report-test: UriScan:(180628864354917)(9452136761055)(85827821059158)(258649278758335)(192813158149592); x-exchange-antispam-report-cfa-test: BCL:0;PCL:0;RULEID:(6040501)(2401047)(5005006)(8121501046)(10201501046)(3002001)(3231101)(2400082)(944501161)(93006095)(93001095)(6055026)(6041288)(20161123560045)(201703131423095)(201702281528075)(20161123555045)(201703061421075)(201703061406153)(20161123562045)(20161123564045)(20161123558120)(6072148)(201708071742011);SRVR:DM2PR0201MB1040;BCL:0;PCL:0;RULEID:;SRVR:DM2PR0201MB1040; x-forefront-prvs: 0570F1F193 x-microsoft-antispam-message-info: STXs+CWN4ErCbMIGUnkh0kSOtRcCu3dhIwTY+D957I/1AWJBD9arLlXGjkKJzwfsJPmSOL4vyRv/yczEwJArbQ== spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: afc314d4-eb76-4ae7-7f23-08d569cf13cb X-MS-Exchange-CrossTenant-originalarrivaltime: 01 Feb 2018 23:54:05.2480 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM2PR0201MB1040 X-getmail-retrieved-from-mailbox: INBOX X-GMAIL-THRID: =?utf-8?q?1590517939735530008?= X-GMAIL-MSGID: =?utf-8?q?1591244750876892381?= X-Mailing-List: linux-kernel@vger.kernel.org List-ID: Hi Mark, > -----Original Message----- > From: Mark Rutland [mailto:mark.rutland@arm.com] > Sent: Thursday, February 01, 2018 2:33 AM > To: Jolly Shah > Cc: ard.biesheuvel@linaro.org; mingo@kernel.org; > gregkh@linuxfoundation.org; matt@codeblueprint.co.uk; > sudeep.holla@arm.com; hkallweit1@gmail.com; keescook@chromium.org; > dmitry.torokhov@gmail.com; michal.simek@xilinx.com; robh+dt@kernel.org; > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org; > devicetree@vger.kernel.org; Rajan Vaja > Subject: Re: [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP firmwar= e > driver >=20 > On Thu, Feb 01, 2018 at 01:23:48AM +0000, Jolly Shah wrote: > > Hi Mark, > > Thanks for the review, > > > > > -----Original Message----- > > > From: Mark Rutland [mailto:mark.rutland@arm.com] > > > Sent: Wednesday, January 31, 2018 10:20 AM > > > To: Jolly Shah > > > Cc: ard.biesheuvel@linaro.org; mingo@kernel.org; > > > gregkh@linuxfoundation.org; matt@codeblueprint.co.uk; > > > sudeep.holla@arm.com; hkallweit1@gmail.com; keescook@chromium.org; > > > dmitry.torokhov@gmail.com; michal.simek@xilinx.com; > > > robh+dt@kernel.org; linux-arm-kernel@lists.infradead.org; > > > linux-kernel@vger.kernel.org; devicetree@vger.kernel.org; Jolly Shah > > > ; Rajan Vaja > > > Subject: Re: [PATCH v3 2/4] drivers: firmware: xilinx: Add ZynqMP > > > firmware driver > > > > > > On Wed, Jan 24, 2018 at 03:21:12PM -0800, Jolly Shah wrote: > > > > This patch is adding communication layer with firmware. > > > > Firmware driver provides an interface to firmware APIs. > > > > Interface APIs can be used by any driver to communicate to > > > > PMUFW(Platform Management Unit). All requests go through ATF. > > > > > > > +/** > > > > + * zynqmp_pm_set_wakeup_source - PM call to specify the wakeup > source > > > > + * while suspended > > > > + * @target: Node ID of the targeted PU or subsystem > > > > + * @wakeup_node:Node ID of the wakeup peripheral > > > > + * @enable: Enable or disable the specified peripheral as wake > source > > > > + * > > > > + * Return: Returns status, either success or error+reason > > > > + */ > > > > +static int zynqmp_pm_set_wakeup_source(const u32 target, > > > > + const u32 wakeup_node, > > > > + const u32 enable) > > > > +{ > > > > + return invoke_pm_fn(PM_SET_WAKEUP_SOURCE, target, > > > > + wakeup_node, enable, 0, NULL); } > > > > > > I see many functions take a "Node ID" parameter, but these don't > > > appear to be in any DT binding, and drivers (other than the debugfs d= river) > aren't using them. > > > > > > What's the plan for making use of these? Where are the node IDs > > > going to come from in practice? > > > > > Node ids are defined in firmware.h. Node id refers to targeted > PU/subsystem/peripheral for required action. >=20 > Ok. What I was asking was how a node id would be associated with particul= ar > peripheral instances (which are presumably going to be nodes in the DT). >=20 > e.g. if I have >=20 > device@foo { > compatible =3D "xlnx,some-device"; > reg =3D <0xf00 0x100>; > ... > }; >=20 > ... how does the kernel know which node id(s) the device is associated wi= th? >=20 > I assume that those will need something like a xlnx,eemi-node-id property= . >=20 > [...] >=20 ZynqMP Power domain driver has node-ids defines under pd-id properties.(RFC= patch below) https://patchwork.kernel.org/patch/10150683/ Individual driver can have phandle to it. For example, power-domains { pd_xx: pd_xx { #power-domain-cells =3D <0x0>; pd-id =3D <0x7>; }; pd_yy: pd_yy { #power-domain-cells =3D <0x0>; pd-id =3D <0xf>; }; }; device: dev@ffe00000 { compatible =3D "dev"; reg =3D <0x0 0xFFE00000 0x0 0x20000>; pd-handle =3D <&pd_xx>; }; > > > > +/** > > > > + * zynqmp_pm_pinctrl_request - Request Pin from firmware > > > > + * @pin: Pin number to request > > > > + * > > > > > > No DT binding for the pinctrl bits? > > > > > > [...] > > It doesn't require any bindings. Calling drivers will have DT binding f= or pins they > use. >=20 > For those drivers to be able to refer to the EEMI FW as a pin controller,= we'll > need a pinctrl node in the DT (and hence a binding). >=20 This is just an interface driver. There is a separate pinctrl and clock dri= ver who will use these APIs to communicate with PMU(Platform Management Uni= t). Those driver has required DT nodes and bindings to use these APIs. For example, Clock driver bindings are mentioned below: https://patchwork.kernel.org/patch/10150703/ > > > > +/** > > > > + * zynqmp_pm_clock_enable - Enable the clock for given id > > > > + * @clock_id: ID of the clock to be enabled > > > > + * > > > > > > Likewise for the clocks? > > > > > It doesn't require bindings too. >=20 > As with pinctrl, for drivers to be able to refer to these clocks, we'll n= eed a clock > node in the DT (and hence a binding). >=20 > Thanks, > Mark.