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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6158.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: eaedaa3e-b1e9-4168-4233-08dde1643b80 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2025 10:11:16.7502 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 0Ve/mZXWBns++uHSv056QLJJies6bUycaLoaOsyYfY7I8vGQfNxIjVr1Lc63RwLdLeM/xZz5kgu2s3u5b0cEOg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB8525 [AMD Official Use Only - AMD Internal Distribution Only] Hi Bjorn, > -----Original Message----- > From: Bjorn Helgaas > Sent: Wednesday, August 13, 2025 1:11 AM > To: Musham, Sai Krishna > Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; mani@kernel= .org; > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; cassel@kernel.o= rg; > linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; Simek, Michal ; Gogada, Bha= rat > Kumar ; Havalige, Thippeswamy > > Subject: Re: [PATCH v7 2/2] PCI: amd-mdb: Add support for PCIe RP PERST# > signal handling > > Caution: This message originated from an External Source. Use proper caut= ion > when opening attachments, clicking links, or responding. > > > On Thu, Aug 07, 2025 at 01:10:19PM +0530, Sai Krishna Musham wrote: > > Add support for handling the AMD Versal Gen 2 MDB PCIe Root Port PERST# > > signal via a GPIO by parsing the new PCIe bridge node to acquire the > > reset GPIO. If the bridge node is not found, fall back to acquiring it > > from the PCIe host bridge node. > > > > As part of this, update the interrupt controller node parsing to use > > of_get_child_by_name() instead of of_get_next_child(), since the PCIe > > host bridge node now has multiple children. This ensures the correct > > node is selected during initialization. > > > > Signed-off-by: Sai Krishna Musham > > --- > > Changes in v7: > > - Use for_each_child_of_node_with_prefix() to iterate through PCIe > > Bridge nodes. > > > > Changes in v6: > > - Simplified error checking condition logic. > > - Removed unnecessary fallback message. > > > > Changes in v5: > > - Add fall back mechanism to acquire reset GPIO from PCIe node when PCI= e > Bridge > > node is not present. > > > > Changes in v4: > > - Resolve kernel test robot warning. > > https://lore.kernel.org/oe-kbuild-all/202506241020.rPD1a2Vr-lkp@intel.c= om/ > > - Update commit message. > > > > Changes in v3: > > - Implement amd_mdb_parse_pcie_port to parse bridge node for reset-gpio= s > property. > > > > Changes in v2: > > - Change delay to PCIE_T_PVPERL_MS > > > > v6 https://lore.kernel.org/all/20250719030951.3616385-1- > sai.krishna.musham@amd.com/ > > v5 https://lore.kernel.org/all/20250711052357.3859719-1- > sai.krishna.musham@amd.com/ > > v4 https://lore.kernel.org/all/20250626054906.3277029-1- > sai.krishna.musham@amd.com/ > > v3 https://lore.kernel.org/r/20250618080931.2472366-1- > sai.krishna.musham@amd.com/ > > v2 https://lore.kernel.org/r/20250429090046.1512000-1- > sai.krishna.musham@amd.com/ > > v1 https://lore.kernel.org/r/20250326041507.98232-1- > sai.krishna.musham@amd.com/ > > --- > > drivers/pci/controller/dwc/pcie-amd-mdb.c | 52 ++++++++++++++++++++++- > > 1 file changed, 51 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/pci/controller/dwc/pcie-amd-mdb.c > b/drivers/pci/controller/dwc/pcie-amd-mdb.c > > index 9f7251a16d32..3c6e837465bb 100644 > > --- a/drivers/pci/controller/dwc/pcie-amd-mdb.c > > +++ b/drivers/pci/controller/dwc/pcie-amd-mdb.c > > @@ -18,6 +18,7 @@ > > #include > > #include > > > > +#include "../../pci.h" > > #include "pcie-designware.h" > > > > #define AMD_MDB_TLP_IR_STATUS_MISC 0x4C0 > > @@ -56,6 +57,7 @@ > > * @slcr: MDB System Level Control and Status Register (SLCR) base > > * @intx_domain: INTx IRQ domain pointer > > * @mdb_domain: MDB IRQ domain pointer > > + * @perst_gpio: GPIO descriptor for PERST# signal handling > > * @intx_irq: INTx IRQ interrupt number > > */ > > struct amd_mdb_pcie { > > @@ -63,6 +65,7 @@ struct amd_mdb_pcie { > > void __iomem *slcr; > > struct irq_domain *intx_domain; > > struct irq_domain *mdb_domain; > > + struct gpio_desc *perst_gpio; > > int intx_irq; > > }; > > > > @@ -284,7 +287,7 @@ static int amd_mdb_pcie_init_irq_domains(struct > amd_mdb_pcie *pcie, > > struct device_node *pcie_intc_node; > > int err; > > > > - pcie_intc_node =3D of_get_next_child(node, NULL); > > + pcie_intc_node =3D of_get_child_by_name(node, "interrupt-controll= er"); > > if (!pcie_intc_node) { > > dev_err(dev, "No PCIe Intc node found\n"); > > return -ENODEV; > > @@ -402,6 +405,28 @@ static int amd_mdb_setup_irq(struct amd_mdb_pcie > *pcie, > > return 0; > > } > > > > +static int amd_mdb_parse_pcie_port(struct amd_mdb_pcie *pcie) > > +{ > > + struct device *dev =3D pcie->pci.dev; > > + struct device_node *pcie_port_node __maybe_unused; > > + > > + /* > > + * This platform currently supports only one Root Port, so the lo= op > > + * will execute only once. > > + * TODO: Enhance the driver to handle multiple Root Ports in the = future. > > + */ > > + for_each_child_of_node_with_prefix(dev->of_node, pcie_port_node, = "pcie") { > > This is only the second user of for_each_child_of_node_with_prefix() > in the whole tree. Also the only use of "__maybe_unused" in > drivers/pci/controller/. > > Most of the PCI controller drivers use > for_each_available_child_of_node_scoped(); can we do the same here? > > The apple, kirin, mt7621, mtk, and qcom drivers are examples. I think > the qcom structure is pretty good, and it has a similar fallback path > for DTs without Root Port nodes (qcom_pcie_parse_legacy_binding()): > > qcom_pcie_probe > ret =3D qcom_pcie_parse_ports > for_each_available_child_of_node_scoped(dev->of_node, of_port) > qcom_pcie_parse_port(of_port) > reset =3D devm_fwnode_gpiod_get(..., "reset", ...) > if (ret) > qcom_pcie_parse_legacy_binding > > IIUC the current amd-mdb hardware only supports a single Root Port, so > I don't think you need a TODO, since there's no point in that > enhancement until hardware supports multiple RPs. > > But I probably *would* add a check here so that if we run the current > driver on future hardware that does have multiple Root Ports with > separate resets for each RP, there's at least a chance that the first > RP will work. E.g., > > amd_mdb_parse_pcie_port(...) > { > if (pcie->perst_gpio) { > dev_warn("Ignoring extra Root Port\n"); > return 0; > } > > pcie->perst_gpio =3D devm_fwnode_gpiod_get(...); > Thanks for the feedback. I'll switch to using for_each_available_child_of_n= ode_scoped() and send it as a separate patch. > > + pcie->perst_gpio =3D devm_fwnode_gpiod_get(dev, > of_fwnode_handle(pcie_port_node), > > + "reset", GPIOD_O= UT_HIGH, NULL); > > + if (IS_ERR(pcie->perst_gpio)) > > + return dev_err_probe(dev, PTR_ERR(pcie->perst_gpi= o), > > + "Failed to request reset GPI= O\n"); > > + return 0; > > + } > > + > > + return -ENODEV; > > +} > > + > > static int amd_mdb_add_pcie_port(struct amd_mdb_pcie *pcie, > > struct platform_device *pdev) > > { > > @@ -426,6 +451,12 @@ static int amd_mdb_add_pcie_port(struct > amd_mdb_pcie *pcie, > > > > pp->ops =3D &amd_mdb_pcie_host_ops; > > > > + if (pcie->perst_gpio) { > > + mdelay(PCIE_T_PVPERL_MS); > > + gpiod_set_value_cansleep(pcie->perst_gpio, 0); > > + mdelay(PCIE_RESET_CONFIG_WAIT_MS); > > + } > > + > > err =3D dw_pcie_host_init(pp); > > if (err) { > > dev_err(dev, "Failed to initialize host, err=3D%d\n", err= ); > > @@ -444,6 +475,7 @@ static int amd_mdb_pcie_probe(struct platform_devic= e > *pdev) > > struct device *dev =3D &pdev->dev; > > struct amd_mdb_pcie *pcie; > > struct dw_pcie *pci; > > + int ret; > > > > pcie =3D devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); > > if (!pcie) > > @@ -454,6 +486,24 @@ static int amd_mdb_pcie_probe(struct platform_devi= ce > *pdev) > > > > platform_set_drvdata(pdev, pcie); > > > > + ret =3D amd_mdb_parse_pcie_port(pcie); > > + /* > > + * If amd_mdb_parse_pcie_port returns -ENODEV, it indicates that = the > > + * PCIe Bridge node was not found in the device tree. This is not > > + * considered a fatal error and will trigger a fallback where the > > + * reset GPIO is acquired directly from the PCIe Host Bridge node= . > > + */ > > + if (ret) { > > + if (ret !=3D -ENODEV) > > + return ret; > > + > > + pcie->perst_gpio =3D devm_gpiod_get_optional(dev, "reset"= , > > + GPIOD_OUT_HIGH= ); > > + if (IS_ERR(pcie->perst_gpio)) > > + return dev_err_probe(dev, PTR_ERR(pcie->perst_gpi= o), > > + "Failed to request reset GPI= O\n"); > > + } > > + > > return amd_mdb_add_pcie_port(pcie, pdev); > > } > > > > -- > > 2.43.0 > >