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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DM4PR12MB6158.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: ff21e03a-c2e7-4819-15f3-08ddadb692f3 X-MS-Exchange-CrossTenant-originalarrivaltime: 17 Jun 2025 15:49:41.7091 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: XcVSaB/6SYBkx+p7oc2bY7ZeltIs6QnMrAtGj9uMnqUkj15HOrg4CZZBQ84mgQCop768ZobMhyy9J/EYhcYDpg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SA3PR12MB7923 [AMD Official Use Only - AMD Internal Distribution Only] Hi Bjorn, > -----Original Message----- > From: Bjorn Helgaas > Sent: Tuesday, June 17, 2025 8:17 PM > To: Musham, Sai Krishna > Cc: Manivannan Sadhasivam ; bhelgaas@google.com; > lpieralisi@kernel.org; kw@linux.com; manivannan.sadhasivam@linaro.org; > robh@kernel.org; krzk+dt@kernel.org; conor+dt@kernel.org; cassel@kernel.o= rg; > linux-pci@vger.kernel.org; devicetree@vger.kernel.org; linux- > kernel@vger.kernel.org; Simek, Michal ; Gogada, Bha= rat > Kumar ; Havalige, Thippeswamy > > Subject: Re: [RESEND PATCH v7 2/2] PCI: xilinx-cpm: Add support for PCIe = RP > PERST# signal > > Caution: This message originated from an External Source. Use proper caut= ion > when opening attachments, clicking links, or responding. > > > On Tue, Jun 17, 2025 at 04:14:37AM +0000, Musham, Sai Krishna wrote: > > [AMD Official Use Only - AMD Internal Distribution Only] > > > > Hi Manivannan, > > > > > -----Original Message----- > > > From: Manivannan Sadhasivam > > > Sent: Thursday, June 12, 2025 10:49 PM > > > To: Musham, Sai Krishna > > > Cc: bhelgaas@google.com; lpieralisi@kernel.org; kw@linux.com; > > > manivannan.sadhasivam@linaro.org; robh@kernel.org; krzk+dt@kernel.org= ; > > > conor+dt@kernel.org; cassel@kernel.org; linux-pci@vger.kernel.org; > > > devicetree@vger.kernel.org; linux-kernel@vger.kernel.org; Simek, Mich= al > > > ; Gogada, Bharat Kumar > > > ; Havalige, Thippeswamy > > > > > > Subject: Re: [RESEND PATCH v7 2/2] PCI: xilinx-cpm: Add support for P= CIe RP > > > PERST# signal > > > > > > Caution: This message originated from an External Source. Use proper = caution > > > when opening attachments, clicking links, or responding. > > > > > > > > > On Mon, Apr 14, 2025 at 08:53:04AM +0530, Sai Krishna Musham wrote: > > > > Add support for handling the PCIe Root Port (RP) PERST# signal usin= g > > > > the GPIO framework, along with the PCIe IP reset. This reset is > > > > managed by the driver and occurs after the Initial Power Up sequenc= e > > > > (PCIe CEM r6.0, 2.2.1) is handled in hardware before the driver's p= robe > > > > function is called. > > > > > + if (do_reset) { > > > > + /* Assert the PCIe IP reset */ > > > > + writel_relaxed(0x1, port->crx_base + variant->cpm_pci= e_rst); > > > > + > > > > + /* > > > > + * "PERST# active time", as per Table 2-10: Power Seq= uencing > > > > + * and Reset Signal Timings of the PCIe Electromechan= ical > > > > + * Specification, Revision 6.0, symbol "T_PERST". > > > > + */ > > > > + udelay(100); > > > > > > Are you sure that you need T_PERST here and not T_PVPERL? T_PERST > > > is only valid while resuming from D3Cold i.e., after power up, > > > while T_PVPERL is valid during the power up, which is usually the > > > case when a controller driver probes. Is your driver relying on > > > power being enabled by the bootloader and the driver just toggling > > > PERST# to perform conventional reset of the endpoint? > > > > Thanks for pointing that out. Yes, the power-up sequence is handled > > by the hardware, and the driver relies on power being enabled by it. > > We're only toggling the PERST# signal in the driver to perform a > > conventional reset of the endpoint. So, I'm confident that T_PERST > > is the appropriate timing reference here, not T_PVPERL. > > > > Additionally, this delay was recommended by our hardware team, who > > confirmed that the power-up sequence is managed in hardware logic, > > and that T_PERST is the appropriate timing to apply in this context. > > > > I also checked pci.h but couldn't find a predefined macro for > > T_PERST, so I used 100. Please let me know if there's a preferred > > macro I should be using instead. > > If we need a new macro, please add it. Include a citation to the > relevant section of the spec ("PCIe CEM r6.0, sec 2.11.2"; table > numbers don't appear in the table of contents so they're hard to > find), and include the units ("_US", I guess) in the macro name. > > Given a comment at the macro definition, you don't need to repeat it > at all the uses. > Thanks for the review, sure I will add new macro and include a citation to the relevant section of the PCIe spec. > Bjorn Thanks, Sai Krishna