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From: "Adrian Schlegel" <me@adrianschlegel.com>
To: "Yazen Ghannam" <yazen.ghannam@amd.com>,
	"Adrian Schlegel" <me@adrianschlegel.com>
Cc: <tony.luck@intel.com>, <bp@alien8.de>, <x86@kernel.org>,
	<linux-edac@vger.kernel.org>, <linux-kernel@vger.kernel.org>,
	<sohil.mehta@intel.com>
Subject: Re: [PATCH v3] x86/mce: Do not treat cache hierarchy errors as memory errors
Date: Mon, 19 Oct 2026 20:34:06 +0200	[thread overview]
Message-ID: <DM914GO4A8WW.Q7YN7ISOQJJI@adrianschlegel.com> (raw)
In-Reply-To: <20261019153207.GA144824@yaz-khff2.amd.com>

On Mon Oct 19, 2026 at 5:32 PM CEST, Yazen Ghannam wrote:
> The SDM also mentions "Extended Memory Errors". I guess these were left
> out before, but should they be included?

I don't think so, since from what I can tell from the Intel SDM (Memory
Controller and Extended Memory Errors), extended memory errors use the
same encoding as normal memory errors, but report errors in memory that
is used as a cache, similar to what cache hierarchy errors do.

I also found this thread, where Tony made the same point:
https://lore.kernel.org/all/SJ1PR11MB60831E048B544C83E845D907FC8DA@SJ1PR11MB6083.namprd11.prod.outlook.com/

Best,
Adrian


  reply	other threads:[~2026-10-19 18:34 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-09-27 15:19 [PATCH] RAS/CEC: Only count corrected DRAM errors on Intel Adrian Schlegel
2026-09-27 18:14 ` Borislav Petkov
2026-09-29 19:01   ` Luck, Tony
2026-10-03 22:20 ` [PATCH v2] x86/mce: Do not treat cache hierarchy errors as memory errors Adrian Schlegel
2026-10-03 23:17   ` Borislav Petkov
2026-10-05 15:30   ` Luck, Tony
2026-10-12 19:33   ` [PATCH v3] " Adrian Schlegel
2026-10-13  0:01     ` Luck, Tony
2026-10-13  1:04     ` Qiuxu (Leo) Zhuo
2026-10-19 15:32     ` Yazen Ghannam
2026-10-19 18:34       ` Adrian Schlegel [this message]
2026-10-19 18:42         ` Yazen Ghannam
2026-10-19 20:45         ` Sohil Mehta
2026-10-19 21:06           ` Luck, Tony

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