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A set_bit_release(), however, > was missing so far. It can be expected to be useful for parties that > need release ordering, but not the stricter full ordering of the other > bit-setting functions. > > Add set_bit_release(). > > Signed-off-by: Philipp Stanner > --- > include/asm-generic/bitops/instrumented-atomic.h | 14 ++++++++++++++ > 1 file changed, 14 insertions(+) > > diff --git a/include/asm-generic/bitops/instrumented-atomic.h b/include/a= sm-generic/bitops/instrumented-atomic.h > index c010d54275e4..fb2d1472fd4d 100644 > --- a/include/asm-generic/bitops/instrumented-atomic.h > +++ b/include/asm-generic/bitops/instrumented-atomic.h > @@ -72,6 +72,20 @@ static __always_inline bool test_and_set_bit(long nr, = volatile unsigned long *ad > return arch_test_and_set_bit(nr, addr); > } > =20 > +/** > + * set_bit_release - Set a bit with release ordering > + * @nr: Bit to set > + * @addr: Address to start counting from > + * > + * This is an atomic ordered operation (implied write memory barrier). > + */ > +static __always_inline void set_bit_release(long nr, volatile unsigned l= ong *addr) > +{ > + kcsan_wmb(); > + instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long)); > + arch_set_bit(nr, addr); This is just wrong. There's no code here that gives you the release semanti= cs. kcsan_wmb() is just an annotation and does nothing. wmb is also not release semantics as it does not order LOAD->STORE. Given that set_bit is a relaxed RMW atomic, you can implement set_bit_relea= se with just smp_mb__before_atomic(); set_bit(nr, addr); Which should be correct, but is too strong on some architectures (like RISC= -V), becuase it will produce a full MB instead. So we can either add release bar= riers (hint: I really like it), or we can add arch_set_bit_release and implement = it per arch; on RISC-V for example it can then be translated to amoor.rl (whic= h is not being produced by any existing bit ops).c Best, Gary > +} > + > /** > * test_and_clear_bit - Clear a bit and return its old value > * @nr: Bit to clear