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>> > + instrument_atomic_write(addr + BIT_WORD(nr), sizeof(long)); >> > + arch_set_bit(nr, addr); >>=20 >> This is just wrong. There's no code here that gives you the release sema= ntics. >>=20 >> kcsan_wmb() is just an annotation and does nothing. wmb is also not rele= ase >> semantics as it does not order LOAD->STORE. > > What are the other functions here then even about? > > /** > * test_and_set_bit - Set a bit and return its old value > * @nr: Bit to set > * @addr: Address to count from > * > * This is an atomic fully-ordered operation (implied full memory barrier= ). > */ > static __always_inline bool test_and_set_bit(long nr, volatile unsigned l= ong *addr) > { > kcsan_mb(); > instrument_atomic_read_write(addr + BIT_WORD(nr), sizeof(long)); > return arch_test_and_set_bit(nr, addr); > } > > Where does the "full ordering" come from? I suppose implied barrier > then means it comes from the architecture's implementation. But what's > then the purpose of kcsan_XX ? It's from arch_test_and_set_bit. KCSAN doesn't see arch code, so the kcsan_mb() and in fact instrumnent_atomic_read_write() both are annotations to indicate that this = is conceptually a mb() + STORE for instrumentation purpose. Best, Gary