From: "Encrow Thorne" <encrow.thorne@linux.spacemit.com>
To: "Manivannan Sadhasivam" <manivannan.sadhasivam@oss.qualcomm.com>,
"Encrow Thorne" <encrow.thorne@linux.spacemit.com>
Cc: "Lorenzo Pieralisi" <lpieralisi@kernel.org>,
"Krzysztof Wilczyński" <kwilczynski@kernel.org>,
"Manivannan Sadhasivam" <mani@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Bjorn Helgaas" <bhelgaas@google.com>,
"Yixun Lan" <dlan@kernel.org>,
"Troy Mitchell" <troy.mitchell@linux.spacemit.com>,
linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org,
spacemit@lists.linux.dev, linux-kernel@vger.kernel.org
Subject: Re: [PATCH] PCI: spacemit: Ignore link partner PERST on K1
Date: Thu, 05 Nov 2026 10:51:35 +0800 [thread overview]
Message-ID: <DMMXQ358UWUZ.35H3HEEEUW1V8@linux.spacemit.com> (raw)
In-Reply-To: <179229759512.2114.3306580489141327360.b4-reply@b4>
On Sun Oct 18, 2026 at 12:26 PM CST, Manivannan Sadhasivam wrote:
> On 2026-09-24 10:04 +0800, Encrow Thorne wrote:
>> The K1 PCIe controller and PHY are affected by the PERST signal from
>> the link partner during initialization. With some devices connected,
>> this can prevent host initialization from progressing and cause the
>> system to hang while probing the PCIe controller.
>>
>> Set PCIE_IGNORE_PERSTN before accessing the DBI registers. When set,
>> this bit makes both the PCIe controller and PHY ignore the PERST
>> signal from the link partner.
>>
>> This allows host initialization to complete without being affected by
>> the link partner's PERST state.
>>
>> Signed-off-by: Encrow Thorne <encrow.thorne@linux.spacemit.com>
>> ---
>> drivers/pci/controller/dwc/pcie-spacemit-k1.c | 8 ++++++++
>> 1 file changed, 8 insertions(+)
>>
>> diff --git a/drivers/pci/controller/dwc/pcie-spacemit-k1.c b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
>> index 0564c46e2f48..98f067e1ba81 100644
>> --- a/drivers/pci/controller/dwc/pcie-spacemit-k1.c
>> +++ b/drivers/pci/controller/dwc/pcie-spacemit-k1.c
>> @@ -44,6 +44,7 @@
>>
>> #define PCIE_CONTROL_LOGIC 0x0004
>> #define PCIE_SOFT_RESET BIT(0)
>> +#define PCIE_IGNORE_PERSTN BIT(2)
>>
>> struct k1_pcie {
>> struct dw_pcie pci;
>> @@ -137,6 +138,13 @@ static int k1_pcie_init(struct dw_pcie_rp *pp)
>> if (ret)
>> return ret;
>>
>> + /*
>> + * When set to 1, the PCIe controller and PHY ignore the PERST signal
>> + * from the link partner in both RC and EP modes.
>> + */
>
Hi Mani
> What? PERST# is an output signal to RC and input to Endpoint. PERST# is not
> controlled by the Endpoint, but only by the RC/host.
>
> - Mani
You are right; my earlier wording was misleading.
On K1, the PERST# pad input feeds back into the local controller's
internal reset input even in RC mode. Thus, the RC can reset itself
when asserting PERST# to reset the endpoint.
PCIE_IGNORE_PERSTN masks this input path without affecting the
RC's control of the external PERST# signal.
Regards,
Encrow Thorne
prev parent reply other threads:[~2026-11-05 2:52 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-09-24 2:04 Encrow Thorne
2026-09-24 2:23 ` Troy Mitchell
2026-11-05 2:53 ` Encrow Thorne
2026-10-18 4:26 ` Manivannan Sadhasivam
2026-11-05 2:51 ` Encrow Thorne [this message]
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