On Fri, 6 Nov 2026 14:05:24 +0800, Jiayu Du wrote:
> Add read-only NVMEM access to bank 0 and bank 7 of the SpacemiT K3
> eFuse controller. These banks contain temperature calibration
> parameters and other configuration data.
The rest of the window holds the root key and the SSK, which is why
only these two banks are exposed. Please say so here and in a comment
above k3_efuse_keepouts.

> Snapshot the shadow registers with aligned 32-bit reads and expose the
> data in little-endian order at controller-relative offsets. Serve
> reads from the snapshot and use keepouts for the remaining register
> ranges. Keep the AES_WTM clock enabled and its shared reset deasserted
> while the provider is registered.
Why keep the clock on? Reads are served from the snapshot and nothing
touches the hardware after probe.

Tested on CoM260:
- clock on only around the snapshot: probe and unbind/bind work, the
  clock stays off (AES_CLK_RES_CTRL 0x00c30050), same bank 0/7 data.
- this patch: unbind gates the clock and asserts the reset
  (0x00c30070 -> 0x00c30040), rebind reads the same data.
- this patch: 3s of WTM_RST or of clock gating leaves the shadow
  values and FUSE_READY unchanged.

[...]
>
> +	depends on COMMON_CLK && RESET_CONTROLLER
Not needed, both APIs have stubs.

[...]
>
> +#define K3_EFUSE_REG_SIZE		0x400
> +#define K3_EFUSE_BANK_SIZE		0x20
> +#define K3_EFUSE_BANK0_OFFSET	0x104
> +#define K3_EFUSE_BANK7_OFFSET	0x190
Nit: the last two are not aligned with the others.

[...]
>
> +	if (resource_size(res) != K3_EFUSE_REG_SIZE ||
> +	    res->start % sizeof(u32))
No need to validate DT here. Drop it and use
devm_platform_ioremap_resource().

[...]
>
> +	reset = devm_reset_control_get_shared_deasserted(dev, NULL);
This asserts the reset on unbind, rmmod and probe failure. The fuse
data survives, but WTM_RST resets the whole GEU (FUSE_SCLK_DIV_CNTR
went back to its boot value). The driver does not need the block after
the snapshot, so use devm_reset_control_get_shared() and only
deassert it.

[...]
>
> +		for (i = 0; i < K3_EFUSE_BANK_SIZE; i += sizeof(u32)) {
[...]
> +			put_unaligned_le32(val, efuse->data[bank] + i);
Please poll FUSE_READY (GEU_FUSE_STATUS bit 1, offset 0x184) before
taking the snapshot, and fail the probe if it never sets.

-- 
Troy Mitchell