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[86.49.245.11]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4b76cbe9e31sm198493265e9.2.2026.11.09.05.40.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 09 Nov 2026 05:40:31 -0800 (PST) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list Mime-Version: 1.0 Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; charset=UTF-8 Date: Mon, 09 Nov 2026 14:40:30 +0100 Message-Id: Subject: Re: [PATCH 1/6] riscv: hwprobe: Report FP extensions only when available Cc: "Charlie Jenkins" , , , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" , "Samuel Holland" , "Andy Chiu" , "Zong Li" , "Guodong Xu" To: From: =?utf-8?q?Radim_Kr=C4=8Dm=C3=A1=C5=99?= References: <20261006075303.205216-1-radim.krcmar@oss.qualcomm.com> <20261006075303.205216-2-radim.krcmar@oss.qualcomm.com> <179133089395.137225.157195939155119911.b4-review@b4> In-Reply-To: X-Authority-Analysis: v=2.4 cv=TMjQ2Fla c=1 sm=1 tr=0 ts=6af1cd51 cx=c_pps a=P2rfLEam3zuxRRdjJWA2cw==:117 a=4CXLxsOAgPM/krjtHEZQyA==:17 a=IkcTkHD0fZMA:10 a=zJRp6_cAMcgA:10 a=M51BFTxLslgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=gowsoOTTUOVcmtlkKump:22 a=EUspDBNiAAAA:8 a=pGLkceISAAAA:8 a=7zOU-n4moG5dCeRVheEA:9 a=QEXdDO2ut3YA:10 a=ODZdjJIeia2B_SHc_B0f:22 X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA5MDA1NCBTYWx0ZWRfXy2zmHGloXo0n JkRxyjEdtSPLzv+TehM/Px+h/sE2jpM30bl44MQA05pIYyzOS1r83ShoOOJNEu3+WDPbuHADDhx 6oOWrTabJV94w8nrrb9fBKfK5S0tES+6Pb5sMysbi452u08gw9rWcn66zVq7AsWmrkBmDWagP5k 7gO1x7h2hiLfXWkshF8+AHv68818jD789TlQsaHoiWdzP1vv2T/nTrFEe18Z3v3t4K+1g4s5XPl vyXbmr/+yCwG425LhzkoXZRTd33qdnxOQ0GZ+XeIR2YPBuG3R/zTOkxfxu4olvhYfHlCxJxpk5A weRCuDwLqp6LvrgRZY6alPGXQ4fuwk1KYhDpuW5l/q4xQfPAGgOfAP+xLMOTvb1a0VqV2EaT06x p2WeOztIRgLbsrtcsaw+POfODZc+PwRcVLv2ZRsGKI8yKTfuyFwx58ZeoH8SYAPC8p7PPPC3Vco +QOa3DN6etenA+sq1mA== X-Proofpoint-GUID: kNOfGfCDeaI4K8B0G5-U6xry85HY--FT X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA5MDA1NCBTYWx0ZWRfXwwPg3Entii5H CB8CBcmnzjGpUJz5SylJIh6U6PNCTYvajS1ahOeGvNHhnPUNamZj7tgetLtbHYPhUsEdAJmhdAR dcWF71ZSg3ZYjp0Gx/cyDhS8uAYy2kQ= X-Proofpoint-ORIG-GUID: kNOfGfCDeaI4K8B0G5-U6xry85HY--FT X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-09_05,2026-11-06_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 adultscore=0 lowpriorityscore=0 clxscore=1015 malwarescore=0 phishscore=0 priorityscore=1501 spamscore=0 bulkscore=0 impostorscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611090054 2026-11-07T23:16:20-05:00, : > Hi Radim, > > On 2026-10-07 09:46, Radim Kr=C4=8Dm=C3=A1=C5=99 wrote: >>2026-10-06T16:54:53-07:00, Charlie Jenkins : >>> >>> The vector Kconfig is gated on FPU=3Dy so the vector instructions can't >>> ever be enabled when FPU=3Dn. >> >>Right, I'll make the commit message clearer in v2. >>(Zve32x and hence has_vector() can technically exist without CONFIG_FPU, >> so future implementations might require use to remove the dependency.) >> > > Do you mean dropping "depends on FPU" from RISCV_ISA_V? Today it reads > arch/riscv/Kconfig: > > config RISCV_ISA_V > bool "Vector extension support" > depends on TOOLCHAIN_HAS_V > depends on FPU > > Today that dependency also gates Zve32x, Zve64x, Zvbb, Zvbc and the Zvk*, > none of these touches floating-point state, but they are all being gated > by CONFIG_FPU, that seems not correct. > > I noticed that the _validate() callbacks in today's cpufeature.c for thes= e > non-F (non-D) related extensions are checked against V only, but that > doesn't change the fact that CONFIG_RISCV_ISA_V depends on CONFIG_FPU > (from a commit 3 years ago) in Kconfig. V extension does require F (V is Zve64d and at least 128 bit vlen), but Zve32x that we use for _validate() and has_vector() is a subset of V, so we could have a config for RISCV_ISA_ZVE32X that RISCV_ISA_V depends on. I think it would be cleaner to have the ifdefery use RISCV_ISA_ZVE32X, instead of reinterpreting RISCV_ISA_V to mean the base vector extension. At the moment, I don't know of a requirement to have Linux builds with Vector yet without FPU, so we can postpone the code churn... We do support those F-less vector machines even now, just with a minor overhead of dead FPU code. My patch is only for machines where not all harts have F. Thanks.