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From: "Popov, Pavel E" <pavel.e.popov@intel.com>
To: Leon Romanovsky <leon@kernel.org>
Cc: Bjorn Helgaas <helgaas@kernel.org>,
	Jim Chow <jim.chow@broadcom.com>,
	Bjorn Helgaas <bhelgaas@google.com>,
	Logan Gunthorpe <logang@deltatee.com>,
	Radu Rugina <radu.rugina@broadcom.com>,
	Alexey Makhalov <alexey.makhalov@broadcom.com>,
	Wei Liu <wei.liu@kernel.org>,
	Michael Kelley <mhklinux@outlook.com>,
	Lukas Wunner <lukas@wunner.de>,
	Nathan Ciobanu <nathan.d.ciobanu@linux.intel.com>,
	"bcm-kernel-feedback-list@broadcom.com"
	<bcm-kernel-feedback-list@broadcom.com>,
	"virtualization@lists.linux.dev" <virtualization@lists.linux.dev>,
	"linux-hyperv@vger.kernel.org" <linux-hyperv@vger.kernel.org>,
	"linux-pci@vger.kernel.org" <linux-pci@vger.kernel.org>,
	"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: RE: [PATCH 0/2] PCI/P2PDMA: Allow P2PDMA in VMware and Hyper-V guests on Intel hosts
Date: Mon, 12 Oct 2026 20:01:40 +0000	[thread overview]
Message-ID: <DS7PR11MB60647FA80C6BE1029982222DB29F2@DS7PR11MB6064.namprd11.prod.outlook.com> (raw)
In-Reply-To: <20261012182120.GJ219304@unreal>

> Please read all of my responses. I was explicit about why the check
> inside the guest VM produces random results. However, your responses
> continue to focus on the guest, which is not the problem.

Fair, my earlier replies were about the guest. Taking the host-side
points in turn:

1. Host topology decides P2P, the guest cannot see it, and the patch
   says "yes" for every pair regardless.

   The topology is accounted for where the knowledge is: on the host.
   Which devices land in one VM is decided by the admin, from devices
   VMware has certified for passthrough in the Compatibility Guide,
   and on vSphere 8+ by Device Groups, which hands devices sharing a
   switch or interconnect to a VM as a topology-aware group. Hyper-V
   has no equivalent grouping; DDA is plain passthrough, each device
   assigned to the VM explicitly by the admin.

   The blanket "yes" is not new either. On bare metal the flags = 0
   whitelist entries say "yes" for any pair of Xeon Scalable root
   buses, across sockets, with no knowledge of BIOS P2P settings. And
   cpu_supports_p2pdma() already bypasses the host bridge check for
   AMD Zen on CPUID alone, in guests included. This series gives Intel
   hosts what the tree already does for AMD; if that is unacceptable
   in principle, it is unacceptable for AMD guests today.

2. Regression: consumers that work today via a system-memory fallback
   will take the P2P path and break on hosts that cannot route it.

   A wrong "yes" fails safely: without host-side P2P the request is
   stopped at the host IOMMU, nothing is corrupted, the same exposure
   an AMD guest has today. An unconditional "no" is worse: it blocks
   P2P on every host that does route it, and the guest's answer
   changes nothing about whether the host routes it.

   Xeon Scalable routes P2P between any two root ports, which the
   whitelist already encodes. The only hypervisor-side requirement is
   mapping the peer's MMIO into the VM's IOMMU domain, and that is
   what passthrough P2P support means: on ESXi it was an explicit
   per-VM setting for years and is the default since 9.0; Hyper-V does
   it for devices assigned to the same VM, as tested on Windows Server
   2025. The decision is made on the host; the guest only has to stop
   vetoing it.

3. The hypervisor must describe it, HMAT is the way, NAK to anything
   that does not fix the hypervisor first.

   Agreed HMAT is the right source and should take precedence: consult
   it first, this check only where no HMAT exists. The disagreement is
   on "first". Guests on already shipped ESXi and Hyper-V releases
   will never get HMAT, and those stay in production for years; the
   cover letter's note on the adoption timeline was written with
   VMware's input, and Jim can speak to it. Until a hypervisor emits
   HMAT, this fallback is the only path that works.

Thanks,
Pavel

  reply	other threads:[~2026-10-12 20:01 UTC|newest]

Thread overview: 25+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-10-09 15:40 Pavel Popov
2026-10-09 15:40 ` [PATCH 1/2] PCI/P2PDMA: Allow P2PDMA in VMware " Pavel Popov
2026-10-09 16:38   ` Logan Gunthorpe
2026-10-09 16:49     ` Popov, Pavel E
2026-10-09 15:40 ` [PATCH 2/2] PCI/P2PDMA: Allow P2PDMA in Hyper-V " Pavel Popov
2026-10-09 16:58 ` [PATCH 0/2] PCI/P2PDMA: Allow P2PDMA in VMware and " Bjorn Helgaas
2026-10-09 18:08   ` Leon Romanovsky
2026-10-09 18:21     ` Popov, Pavel E
2026-10-09 18:49       ` Leon Romanovsky
2026-10-09 19:13         ` Popov, Pavel E
2026-10-11  5:47           ` Leon Romanovsky
2026-10-12 14:26             ` Popov, Pavel E
2026-10-12 16:24               ` Leon Romanovsky
2026-10-12 16:45                 ` Popov, Pavel E
2026-10-12 18:21                   ` Leon Romanovsky
2026-10-12 20:01                     ` Popov, Pavel E [this message]
2026-10-13 12:20                       ` Leon Romanovsky
2026-10-16 14:55                         ` Popov, Pavel E
2026-10-16 15:31                           ` Leon Romanovsky
2026-10-16 16:05                             ` Popov, Pavel E
2026-10-16 18:18                               ` Logan Gunthorpe
2026-10-16 19:45                                 ` Popov, Pavel E
2026-10-16 20:12                                   ` Logan Gunthorpe
2026-10-16 22:01                                     ` Popov, Pavel E
2026-10-09 19:12     ` Bjorn Helgaas

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