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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: microchip.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: DSWPR11MB9715.namprd11.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ae024b7-2d5e-426c-ffff-08debbc17ef5 X-MS-Exchange-CrossTenant-originalarrivaltime: 27 May 2026 07:28:06.5979 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 3f4057f3-b418-4d4e-ba84-d55b4e897d88 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: ZPHzmd8JbkbLNeIHzAwmY/d5WbkpyqDH7EmwkGFide57waQCxa+1TtpyOehgHGQXpNyXAqL8hmh3UN8OVm6eWMF+FurpeCgzfw0SDvcrPa8= X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM6PR11MB4627 Hi Andrew, Thanks for the comments. > -----Original Message----- > From: Andrew Lunn > Sent: Thursday, May 14, 2026 6:28 PM > To: Thangaraj Samynathan - I53494 > Cc: netdev@vger.kernel.org; andrew+netdev@lunn.ch; > davem@davemloft.net; edumazet@google.com; kuba@kernel.org; > pabeni@redhat.com; Bryan Whitehead - C21958 > ; UNGLinuxDriver > ; linux@armlinux.org.uk; linux- > kernel@vger.kernel.org > Subject: Re: [PATCH v4 3/5] net: lan743x: Add support to software-nodes f= or > SFP >=20 > EXTERNAL EMAIL: Do not click links or open attachments unless you know th= e > content is safe >=20 > > +#define PCI11X1X_TX_FAULT_GPIO 46 > > +#define PCI11X1X_TX_DIS_GPIO 47 > > +#define PCI11X1X_RATE_SEL0_GPIO 48 > > +#define PCI11X1X_LOS_GPIO 49 > > +#define PCI11X1X_MOD_DEF0_GPIO 51 >=20 > How do you know these values? >=20 > Can i buy this device, design my own board, and decide to use a different > mapping of GPIO pins to SFP cage pins? Or does the data sheet say you MUS= T > use this mapping? >=20 > Maybe consider drivers/misc/lan966x_pci.dtso. [Thangaraj Samynathan] ] These values are from the Microchip EVB reference= design, not mandated by the datasheet. A board designer is free to wire SFP signa= ls to different GPIO pins. However, the PCI11x1x is a PCIe add-in card that can also be used in standard x86 systems. A .dtso overlay has no base DT to attach to on x86, and ACPI _DSD properties require the platform firmware vendor to add them - which is not realistic for a PCIe add-in card in the field. We propose using the EVB default GPIO values as a fallback when no firmware description is present, and reading from DT/ACPI _DSD when available. Does this approach seem reasonable? =20 >=20 > Andrew