From: Philip Blundell <pb@nexus.co.uk>
To: Alan Arolovitch <alan@gravity-cs.com>
Cc: linux-kernel@vger.rutgers.edu
Subject: Re: DMA bus-master writes & CPU cache question
Date: Mon, 12 Jul 1999 12:51:37 +0100 [thread overview]
Message-ID: <E113ecT-0006RE-00@fountain.nexus.co.uk> (raw)
In-Reply-To: Your message of "Mon, 12 Jul 1999 02:07:52 +0300." <199907112307.CAA18191@gravity-cs.com>
>Should CPU cache affect reading data from the DMA area, i.e.
>may some buffering effect or data inconherence appear? If so,
>what are the options?
This depends on your architecture. Intel platforms are fully DMA coherent;
the chipset snoops on DMA cycles and flushes the cache as required to maintain
a consistent view. On some other machines this is not the case and you must
deal with the caches by hand (see, for example,
include/asm-arm/proc-armv/io.h).
p.
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prev parent reply other threads:[~1999-07-12 14:57 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
1999-07-11 23:07 Alan Arolovitch
1999-07-12 11:51 ` Philip Blundell [this message]
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