From: Alan Cox <alan@lxorguk.ukuu.org.uk>
To: walters@cis.ohio-state.edu (Colin Walters)
Cc: linux-kernel@vger.kernel.org
Subject: Re: eepro100 (PCI ID 82820) lockups/failure
Date: Mon, 6 Aug 2001 20:14:18 +0100 (BST) [thread overview]
Message-ID: <E15TppS-0001bj-00@the-village.bc.nu> (raw)
In-Reply-To: <873d75janh.church.of.emacs@space-ghost.verbum.org> from "Colin Walters" at Aug 06, 2001 02:39:14 PM
> Shouldn't a udelay(1) always take one microsecond, regardless of
> hardware optimizations?
A udelay(1) should always take 1 microsecond or a bit longer. There are some
funnies with PCI posting to beware of - notably
writel(0x1, foo->reg);
udelay(1);
writel(0x0, foo->reg)
Does _not_ guarantee the two writes hit the PCI device with a 1 uS delay
where its PCI access timing that matters you need to do
writel(0x1, foo->reg)
readl(foo->somethingthatdoesnothing);
udelay(1);
writel(0x0, foo->reg)
next prev parent reply other threads:[~2001-08-06 19:13 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2001-08-04 6:06 Colin Walters
2001-08-06 9:27 ` Andrey Savochkin
2001-08-06 15:48 ` Joseph Cheek
2001-08-07 10:48 ` Andrey Savochkin
2001-08-07 16:35 ` Joseph Cheek
2001-08-06 18:39 ` Colin Walters
2001-08-06 19:00 ` Richard B. Johnson
2001-08-07 10:24 ` Andrey Savochkin
2001-08-07 12:11 ` Richard B. Johnson
2001-08-06 19:14 ` Alan Cox [this message]
2001-08-07 10:46 ` Andrey Savochkin
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