From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id ; Fri, 25 Oct 2002 19:44:37 -0400 Received: (majordomo@vger.kernel.org) by vger.kernel.org id ; Fri, 25 Oct 2002 19:44:37 -0400 Received: from dsl-213-023-039-129.arcor-ip.net ([213.23.39.129]:26284 "EHLO starship") by vger.kernel.org with ESMTP id ; Fri, 25 Oct 2002 19:44:36 -0400 Content-Type: text/plain; charset=US-ASCII From: Daniel Phillips To: "Nakajima, Jun" , Jeff Garzik , Robert Love Subject: Re: [PATCH] hyper-threading information in /proc/cpuinfo Date: Sat, 26 Oct 2002 01:51:25 +0200 X-Mailer: KMail [version 1.3.2] Cc: Alan Cox , "Nakajima, Jun" , "'Dave Jones'" , "'akpm@digeo.com'" , "'linux-kernel@vger.kernel.org'" , "'chrisl@vmware.com'" , "'Martin J. Bligh'" References: In-Reply-To: MIME-Version: 1.0 Content-Transfer-Encoding: 7BIT Message-Id: Sender: linux-kernel-owner@vger.kernel.org X-Mailing-List: linux-kernel@vger.kernel.org On Saturday 26 October 2002 00:42, Nakajima, Jun wrote: > The notion of "SMT (Simultaneous Multi-Threaded)" architecture has been > there for a while (at least 8 years, as far as I know). You would get tons > of info if you search it in Internet. Actually, what we were referring to is multiple complete, separate processor cores on one chip. Two complete cores turns in true 2X performance, modulo cache effects, vs SMT which turns in anywhere from 0 to 20% improvement. MIPS does 2X processors/chip, and IBM is planning to do 32X. I've heard rumours of 128X as well. -- Daniel