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Mon, 05 Feb 2024 23:53:36 -0800 (PST) X-Forwarded-Encrypted: i=0; AJvYcCUCzbly27GvMKMmnHbmpUcxQJNeYbM47wEtSHLWabBiurZKyKWh49Lz4iBP4jbXue+rmAlQwV/GUKAZVhSZYzoNp/PSnkviJ5DZIhCznLX+ZqBW5kL3E58zGL4IhmL2cjYNXFOEbOnvVpAuTfWZhZ8vcYtsQLeO1eDr3zWM66TVUdfc5P7MS1R+MpUnxjlIxGLzU7uy289P73Xeo/WSW2L38L/r+cJ92XOfzD2cWga6qtZFC4JTyCgEn0+5cIMy+P9SWvxzYE/GYA95GjjXrrRG8Tp08gxzZg3dtLiJzGQa+6GJKpXPcs+hcMMXQzm4xEyAfUsJiMF3Q7uTIT8OdpVVNlawYaJImFVJ66cb4E2hypzDnq5yZ0NePmDdlkNmtKfB5mWagTYqwV0eYePM2EnBh8Rk0j6CX8W360MJ5ic7spXAFvsjGh4XVbCAYkKph5VoFAf+bf14DtFpXAGGb0qrMN4FSKw= Received: from smtpclient.apple ([167.99.200.149]) by smtp.gmail.com with ESMTPSA id n29-20020a05600c3b9d00b0040ef2e7041esm1093717wms.6.2024.02.05.23.53.34 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Mon, 05 Feb 2024 23:53:36 -0800 (PST) Content-Type: text/plain; charset=utf-8 Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3774.400.31\)) Subject: Re: [PATCHv1 3/5] arm64: dts: amlogic: Add cache information to the Amlogic G12A SoCS From: Christian Hewitt In-Reply-To: <4248e19e-5f2f-4e4f-a869-a0fec81b16bd@lexina.in> Date: Tue, 6 Feb 2024 11:53:22 +0400 Cc: Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Kevin Hilman , Jerome Brunet , Martin Blumenstingl , devicetree , linux-arm-kernel@lists.infradead.org, AML , LKML , Viacheslav Content-Transfer-Encoding: quoted-printable Message-Id: References: <20240205171930.968-1-linux.amoon@gmail.com> <20240205171930.968-4-linux.amoon@gmail.com> <4248e19e-5f2f-4e4f-a869-a0fec81b16bd@lexina.in> To: Anand Moon X-Mailer: Apple Mail (2.3774.400.31) > On 6 Feb 2024, at 11:48=E2=80=AFam, Viacheslav = wrote: >=20 > You missed the AXG family with the Cortex-A53 CPU. The datasheet does = not provide information on cache sizes. Given that the A113X/A113D are = equipped with the Arm Cortex-A53 processor, it is assumed they use the = same cache size as the S905/S905X/S905X2 models. GXM is also missing, and also using A53 cores. Christian > 05/02/2024 20.19, Anand Moon wrote: >> As per the S905X2 datasheet add missing cache information to the = Amlogic >> G12A SoC. >> - Each Cortex-A53 core has 32KB of L1 instruction cache available and >> 32KB of L1 data cache available. >> - Along with 512KB Unified L2 cache. >> To improve system performance. >> Signed-off-by: Anand Moon >> --- >> No public dataheet available, since S905X2 support Arm Cortex-A53 cpu >> nence used the same cache size as S905 and S905X. >> --- >> arch/arm64/boot/dts/amlogic/meson-g12a.dtsi | 27 = +++++++++++++++++++++ >> 1 file changed, 27 insertions(+) >> diff --git a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi = b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> index 543e70669df5..6e1e3a3f5f18 100644 >> --- a/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> +++ b/arch/arm64/boot/dts/amlogic/meson-g12a.dtsi >> @@ -17,6 +17,12 @@ cpu0: cpu@0 { >> compatible =3D "arm,cortex-a53"; >> reg =3D <0x0 0x0>; >> enable-method =3D "psci"; >> + d-cache-line-size =3D <32>; >> + d-cache-size =3D <0x8000>; >> + d-cache-sets =3D <32>; >> + i-cache-line-size =3D <32>; >> + i-cache-size =3D <0x8000>; >> + i-cache-sets =3D <32>; >> next-level-cache =3D <&l2>; >> #cooling-cells =3D <2>; >> }; >> @@ -26,6 +32,12 @@ cpu1: cpu@1 { >> compatible =3D "arm,cortex-a53"; >> reg =3D <0x0 0x1>; >> enable-method =3D "psci"; >> + d-cache-line-size =3D <32>; >> + d-cache-size =3D <0x8000>; >> + d-cache-sets =3D <32>; >> + i-cache-line-size =3D <32>; >> + i-cache-size =3D <0x8000>; >> + i-cache-sets =3D <32>; >> next-level-cache =3D <&l2>; >> #cooling-cells =3D <2>; >> }; >> @@ -35,6 +47,12 @@ cpu2: cpu@2 { >> compatible =3D "arm,cortex-a53"; >> reg =3D <0x0 0x2>; >> enable-method =3D "psci"; >> + d-cache-line-size =3D <32>; >> + d-cache-size =3D <0x8000>; >> + d-cache-sets =3D <32>; >> + i-cache-line-size =3D <32>; >> + i-cache-size =3D <0x8000>; >> + i-cache-sets =3D <32>; >> next-level-cache =3D <&l2>; >> #cooling-cells =3D <2>; >> }; >> @@ -44,6 +62,12 @@ cpu3: cpu@3 { >> compatible =3D "arm,cortex-a53"; >> reg =3D <0x0 0x3>; >> enable-method =3D "psci"; >> + d-cache-line-size =3D <32>; >> + d-cache-size =3D <0x8000>; >> + d-cache-sets =3D <32>; >> + i-cache-line-size =3D <32>; >> + i-cache-size =3D <0x8000>; >> + i-cache-sets =3D <32>; >> next-level-cache =3D <&l2>; >> #cooling-cells =3D <2>; >> }; >> @@ -52,6 +76,9 @@ l2: l2-cache0 { >> compatible =3D "cache"; >> cache-level =3D <2>; >> cache-unified; >> + cache-size =3D <0x7d000>; /* L2. 512 KB */ >> + cache-line-size =3D <64>; >> + cache-sets =3D <512>; >> }; >> }; >> =20 >=20 >=20 > Best regards, > -- > Viacheslav Bocharov >=20 > _______________________________________________ > linux-amlogic mailing list > linux-amlogic@lists.infradead.org > http://lists.infradead.org/mailman/listinfo/linux-amlogic