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([2402:7500:4ce:5a5b:a845:b3e1:8307:922c]) by smtp.gmail.com with ESMTPSA id b20-20020a63d314000000b005c215baacc1sm28175pgg.70.2023.11.22.11.05.10 (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128); Wed, 22 Nov 2023 11:05:13 -0800 (PST) Content-Type: text/plain; charset=us-ascii Mime-Version: 1.0 (Mac OS X Mail 11.5 \(3445.9.7\)) Subject: Re: [PATCH 12/12] RISC-V: crypto: add Zvkb accelerated ChaCha20 implementation From: Jerry Shih In-Reply-To: <20231122-bulldog-deceased-7e3dadf3a833@spud> Date: Thu, 23 Nov 2023 03:05:08 +0800 Cc: Conor Dooley , Eric Biggers , Paul Walmsley , palmer@dabbelt.com, Albert Ou , herbert@gondor.apana.org.au, davem@davemloft.net, andy.chiu@sifive.com, greentime.hu@sifive.com, guoren@kernel.org, bjorn@rivosinc.com, heiko@sntech.de, ardb@kernel.org, phoebe.chen@sifive.com, hongrong.hsu@sifive.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-crypto@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <20231025183644.8735-1-jerry.shih@sifive.com> <20231025183644.8735-13-jerry.shih@sifive.com> <20231102054327.GH1498@sol.localdomain> <90E2B1B4-ACC1-4316-81CD-E919D3BD03BA@sifive.com> <20231120191856.GA964@sol.localdomain> <9724E3A5-F43C-4239-9031-2B33B72C4EF4@sifive.com> <20231121-knelt-resource-5d71c9246015@wendy> <3BDE7B86-0078-4C77-A383-1C83C88E44DA@sifive.com> <20231122-bulldog-deceased-7e3dadf3a833@spud> To: Conor Dooley X-Mailer: Apple Mail (2.3445.9.7) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Nov 23, 2023, at 02:20, Conor Dooley wrote: > On Thu, Nov 23, 2023 at 01:37:33AM +0800, Jerry Shih wrote: >> On Nov 21, 2023, at 21:14, Conor Dooley = wrote: >>> On Tue, Nov 21, 2023 at 06:55:07PM +0800, Jerry Shih wrote: >>>> Sorry, I just use my `internal` qemu with vector-crypto and rva22 = patches. >>>>=20 >>>> The public qemu haven't supported rva22 profiles. Here is the qemu = patch[1] for >>>> that. But here is the discussion why the qemu doesn't export these >>>> `named extensions`(e.g. Zicclsm). >>>> I try to add Zicclsm in DT in the v2 patch set. Maybe we will have = more discussion >>>> about the rva22 profiles in kernel DT. >>>=20 >>> Please do, that'll be fun! Please take some time to read what the >>> profiles spec actually defines Zicclsm fore before you send those = patches >>> though. I think you might come to find you have misunderstood what = it >>> means - certainly I did the first time I saw it! >>=20 >> =46rom the rva22 profile: >=20 > "rva22" is not a profile. As I pointed out to Eric, this is defined in > the RVA22U64 profile (and the RVA20U64 one, but that is effectively a > moot point). The profile descriptions for these only specify "the ISA > features available to user-mode execution environments", so it is not > suitable for use in any other context. I missed that important part: it's for user space. Thx. >> This requires misaligned support for all regular load and store = instructions (including >> scalar and ``vector``) >>=20 >> The spec includes the explicit `vector` keyword. >> So, I still think we could use Zicclsm checking for these = vector-crypto implementations. >=20 > In userspace, if Zicclsm was exported somewhere, that would be a valid > argument. Even for userspace, the hwprobe flags probably provide more > information though, since the firmware emulation is insanely slow. I agree. It will be more useful to have the flag like = `VECTOR_MISALIGNED_FAST` instead. >> My proposed patch is just a simple patch which only update the DT = document and >> update the isa string parser for Zicclsm. >=20 > Zicclsm has no meaning outside of user mode, so it's not suitable for > use in that context. Other "features" defined in the profiles spec = might > be suitable for inclusion, but it'll be a case-by-case basis. I will skip the Zicclsm part in my v2 patch. >> If it's still not recommend to use Zicclsm >> checking, I will turn to use `RISCV_HWPROBE_MISALIGNED_*` instead. >=20 > Palmer has commented on the rest, so no need for me :) All crypto algorithms will assume that the vector supports misaligned = access in next v2 patch. And the algorithms will also not check for `RISCV_HWPROBE_MISALIGNED_*` = since it's related to scalar accesses. Once we have the vector performance related flag, we could go back here = to use it. -Jerry