Pcie bus enumeration and 64bit issues

[Ruudgoogle <netwerkforens@gmail.com>]

Hello all,

For a big system i use an external pcie enclosure. Unfortunately the bios  fails to properly initialise the system. As work around i plan to start the chassis after the linux kernel has booted. This leads to some other problems i would like to discuss here/get pointers to kernel code to read.

1) the chassis adds several pcie busses, i would like to reserve a range of busnumbers at the last pcie switch in the host. Something like that seems to be done for cardbus, but not for pcie switches in general. The reason is clear: allocating big chunks of busnumbers will exhaust that resource. Looking for advice!

2) For unclear reasons the linux kernel maps the 64bit bars below 4G and that range get exhausted, how can i check if a 64bit mmio pool is present/do i need to specify it manually or should the bios indicate a range? Looking for advice as well.

Ruud