Re: [PATCH 1/2] PCI: dwc: ep: Fix resizable BAR support for multi-PF configurations

[Niklas Cassel <cassel@kernel.org>]

On 22 January 2026 06:05:47 CET, Aksh Garg <a-garg7@ti.com> wrote:
>>> -- 
>>> 2.34.1
>>> 
>> 
>> 
>> Thank you for fixing this!
>> 
>> Reviewed-by: Niklas Cassel <cassel@kernel.org>
>> 
>> 
>> You do need another patch in this series though, that fixes:
>> https://github.com/torvalds/linux/blob/v6.19-rc6/drivers/pci/controller/dwc/pcie-designware-ep.c#L972-L986
>> 
>> As currently, ptm_cap_base is fetched using dw_pcie_find_ext_capability()
>> instead of your new dw_pcie_ep_find_ext_capability() which takes a func_no.
>> 
>
>I examined the register spaces across different PFs to check whether all the PFs have the PTM capability registers, and confirmed that PTM capability registers exist only in PF0. PCIe r6.0 section 7.9.15 'Precision Time Management Extended Capability (PTM Capability)' states that " For Endpoints and Switch Upstream Ports that support PTM, this Capability is required in exactly one Function of the Upstream Port and that Capability controls the PTM behavior of all PTM capable Functions associated with that Upstream Port". This indicates that PTM capabilities are controller-level registers rather than per-function registers. Hence, in my opinion, ptm_cap_base does not require modification, since dw_pcie_find_ext_capability() and dw_pcie_*_dbi() already correctly access PF0's register space, which is the expected behavior for controller-level PTM management.


Hello Aksh,

Thanks a lot for digging in to this.

Since commit:
https://git.kernel.org/pub/scm/linux/kernel/git/pci/pci.git/commit/?h=controller/dwc&id=86291f774fe8524178446cb2c792939640b4970c

Together with your patch,
there will only be a single call site in pcie-designware-ep.c that uses dw_pcie_*_dbi() instead of dw_pcie_ep_*_dbi() remaining.

Thus, I think we should at least add a comment explain why this is the only place in the whole file that can ignore func_no.


Kind regards,
Niklas