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Tue, 25 Apr 2023 05:01:50 -0400 (EDT) Content-Type: text/plain; charset=utf-8 Mime-Version: 1.0 (Mac OS X Mail 16.0 \(3731.500.231\)) Subject: Re: arch/mips/include/asm/timex.h:75:10: error: instruction requires a CPU feature not currently enabled From: Jiaxun Yang In-Reply-To: <20230424200155.GA2605117@dev-arch.thelio-3990X> Date: Tue, 25 Apr 2023 10:01:39 +0100 Cc: Borislav Petkov , kernel test robot , Thomas Bogendoerfer , llvm@lists.linux.dev, oe-kbuild-all@lists.linux.dev, linux-kernel@vger.kernel.org Content-Transfer-Encoding: quoted-printable Message-Id: References: <202304170748.Fg9VIgGd-lkp@intel.com> <20230419223707.GAZEBtE1vZGy5B4EUR@fat_crate.local> <20230419231834.GA1269248@dev-arch.thelio-3990X> <20230424200155.GA2605117@dev-arch.thelio-3990X> To: Nathan Chancellor X-Mailer: Apple Mail (2.3731.500.231) Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > 2023=E5=B9=B44=E6=9C=8824=E6=97=A5 21:01=EF=BC=8CNathan Chancellor = =E5=86=99=E9=81=93=EF=BC=9A >=20 > On Thu, Apr 20, 2023 at 12:41:50AM +0100, Jiaxun Yang wrote: >>=20 >>=20 >>> 2023=E5=B9=B44=E6=9C=8820=E6=97=A5 00:18=EF=BC=8CNathan Chancellor = =E5=86=99=E9=81=93=EF=BC=9A >>>=20 >>> + Jiaxun, who has been looking into MIPS + LLVM issues recently and = has >>> been a big help :) >>=20 >> I think this patch[1] may fix the problem. >=20 > I have the following patch stack: >=20 > $ git log --oneline origin/master^.. > c6cd9f17692e MIPS: Replace assembly isa level directives with macros > 60508ba7d92f MIPS: Limit MIPS_MT_SMP support by ISA reversion > c9e250105de4 MIPS: Fallback CPU -march CFLAG to ISA level if = unsupported > 49c0420e59bb MIPS: Remove cc-option checks for -march=3Docteon > b7ea7e959023 MIPS: Detect toolchain support of o32 ABI with 64 bit CPU > 51f2d93245ba MIPS: Detect toolchain support of workarounds in Kconfig > 7382a07eb105 MIPS: Add toolchain feature dependency for microMIPS = smartMIPS > de0621fbedd3 MIPS: Move various toolchain ASE check to Kconfig > 3b85b9b39960 Add linux-next specific files for 20230424 >=20 > but with the robot's configuration, I still see that error. I notice > that the 'if (sel =3D=3D 0)' branch of ___read_32bit_c0_register() has = no > '.set push' directive, could that matter here? Sorry I was identifying the wrong problem. The real problem is LLVM IAS (or the whole LLVM stack)=E2=80=99s = microMIPS is broken, It unable to handle =E2=80=9Cmfc0=E2=80=9D and many other instructions. Perhaps we should come up a method to block this config to happen. Thanks Jiaxun >=20 > Cheers, > Nathan