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charset="iso-8859-1" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: guidelinegeo.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: GV3P280MB0065.SWEP280.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-Network-Message-Id: a2594e8a-72a9-4ee1-c2c7-08de94afda88 X-MS-Exchange-CrossTenant-originalarrivaltime: 07 Apr 2026 14:13:33.9154 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: f3403a73-63c2-4dc7-b628-287972076881 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: BWyYZWippTFBNWx/3jXOG6AMiwLDVJMuzQrThDwopwwn0abNLEYLCaYw7XeqPTKtRrBGNfVZ2I+YhiKbmfIP9ykJV+TqIxGHp6HSPo9g29UkFTq/lpIbWDup0bj3bgvl X-MS-Exchange-Transport-CrossTenantHeadersStamped: GVYP280MB2271 Hi Salih,=0A= =0A= Thanks for the review.=0A= =0A= Tested on a custom Zynq-7030 board with two TMUX1308APWR analog=0A= multiplexers in dual external mux configuration. The XADC is=0A= instantiated as an AXI XADC Wizard IP with xlnx,external-mux=0A= set to "dual" and xlnx,external-mux-channel set to 1.=0A= =0A= Verified by reading all 16 external mux channels via sysfs=0A= (in_voltageN_raw) and comparing against known reference voltages=0A= on the board. Before the fix, channels routed through ADC-B=0A= returned incorrect values. After the fix, all channels return=0A= the expected voltages matching the board schematic.=0A= =0A= Thanks,=0A= Christofer=0A= ________________________________________=0A= From:=A0Erim, Salih =0A= Sent:=A0Wednesday, April 1, 2026 3:11 PM=0A= To:=A0Simek, Michal ; Jonathan Cameron ; Christofer Jonason ; O'Griofa, C= onall =0A= Cc:=A0lars@metafoo.de ; dlechner@baylibre.com ; nuno.sa@analog.com ; andy@kernel.org ; Victor Jonsson ; linux-iio@v= ger.kernel.org ; linux-arm-kernel@lists.infradea= d.org ; linux-kernel@vger.kernel.org = ; stable@vger.kernel.org =0A= Subject:=A0RE: [PATCH v2] iio: adc: xilinx-xadc: Fix sequencer mode in post= disable for dual mux=0A= =A0=0A= [AMD Official Use Only - AMD Internal Distribution Only]=0A= =0A= Hi Christofer,=0A= =0A= The code change looks correct to me - it aligns postdisable with=0A= preenable by reusing xadc_get_seq_mode(), and the scope is limited=0A= to dual external mux configurations.=0A= =0A= Since this is targeting stable, could you please share what hardware/board= =0A= this was tested on and how you verified that VAUX[8-15] channels=0A= return correct data with the fix applied?=0A= =0A= Reviewed-by: Salih Emin =0A= =0A= Thanks,=0A= Salih=0A= =0A= =0A= > -----Original Message-----=0A= > From: Simek, Michal =0A= > Sent: Tuesday, March 10, 2026 7:43 AM=0A= > To: Jonathan Cameron ; Christofer Jonason=0A= > ; Erim, Salih ;= =0A= > O'Griofa, Conall =0A= > Cc: lars@metafoo.de; dlechner@baylibre.com; nuno.sa@analog.com;=0A= > andy@kernel.org; victor.jonsson@guidelinegeo.com; linux-iio@vger.kernel.o= rg;=0A= > linux-arm-kernel@lists.infradead.org; linux-kernel@vger.kernel.org;=0A= > stable@vger.kernel.org=0A= > Subject: Re: [PATCH v2] iio: adc: xilinx-xadc: Fix sequencer mode in post= disable=0A= > for dual mux=0A= >=0A= > +Salih, Conall,=0A= >=0A= > On 3/7/26 13:41, Jonathan Cameron wrote:=0A= > > On Wed,=A0 4 Mar 2026 10:07:27 +0100=0A= > > Christofer Jonason wrote:=0A= > >=0A= > >> xadc_postdisable() unconditionally sets the sequencer to continuous=0A= > >> mode. For dual external multiplexer configurations this is incorrect:= =0A= > >> simultaneous sampling mode is required so that ADC-A samples through= =0A= > >> the mux on VAUX[0-7] while ADC-B simultaneously samples through the=0A= > >> mux on VAUX[8-15]. In continuous mode only ADC-A is active, so=0A= > >> VAUX[8-15] channels return incorrect data.=0A= > >>=0A= > >> Since postdisable is also called from xadc_probe() to set the initial= =0A= > >> idle state, the wrong sequencer mode is active from the moment the=0A= > >> driver loads.=0A= > >>=0A= > >> The preenable path already uses xadc_get_seq_mode() which returns=0A= > >> SIMULTANEOUS for dual mux. Fix postdisable to do the same.=0A= > >>=0A= > >> Fixes: bdc8cda1d010 ("iio:adc: Add Xilinx XADC driver")=0A= > >> Cc: stable@vger.kernel.org=0A= > >> Signed-off-by: Christofer Jonason=0A= > >> =0A= > >=0A= > > I'll leave this on list for a little longer as I'd really like a=0A= > > confirmation of this one from the AMD Xilinx folk.=0A= >=0A= > Salih/Conall: Please look at this patch and provide your comment or tag.= =0A= >=0A= > Thanks,=0A= > Michal=