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For example, yuv420 is supported but yvu420 is > not. This can be efficiently worked around by just passing the hardware > said chroma planes backwards. Add a flag to the plane state struct and > handling to both tegradc and nvdisplay paths. >=20 > Signed-off-by: Aaron Kling > --- > drivers/gpu/drm/tegra/dc.c | 6 +++++- > drivers/gpu/drm/tegra/hub.c | 14 +++++++++----- > drivers/gpu/drm/tegra/plane.c | 5 ++++- > drivers/gpu/drm/tegra/plane.h | 3 ++- > 4 files changed, 20 insertions(+), 8 deletions(-) >=20 > diff --git a/drivers/gpu/drm/tegra/dc.c b/drivers/gpu/drm/tegra/dc.c > index b0bfa946e6979..39c2e920d76a6 100644 > --- a/drivers/gpu/drm/tegra/dc.c > +++ b/drivers/gpu/drm/tegra/dc.c > @@ -740,7 +740,8 @@ static int tegra_plane_atomic_check(struct drm_plane = *plane, > =20 > err =3D tegra_plane_format(new_plane_state->fb->format->format, > &plane_state->format, > - &plane_state->swap); > + &plane_state->swap, > + &plane_state->swap_uv); > if (err < 0) > return err; > =20 > @@ -872,6 +873,9 @@ static void tegra_plane_atomic_update(struct drm_plan= e *plane, > window.stride[i] =3D fb->pitches[i]; > } > =20 > + if (tegra_plane_state->swap_uv) > + swap(window.base[1], window.base[2]); > + > tegra_dc_setup_window(p, &window); > } > =20 > diff --git a/drivers/gpu/drm/tegra/hub.c b/drivers/gpu/drm/tegra/hub.c > index 448f49f3a7d7e..6427155ac4fdf 100644 > --- a/drivers/gpu/drm/tegra/hub.c > +++ b/drivers/gpu/drm/tegra/hub.c > @@ -440,7 +440,8 @@ static int tegra_shared_plane_atomic_check(struct drm= _plane *plane, > =20 > err =3D tegra_plane_format(new_plane_state->fb->format->format, > &plane_state->format, > - &plane_state->swap); > + &plane_state->swap, > + &plane_state->swap_uv); > if (err < 0) > return err; > =20 > @@ -664,24 +665,27 @@ static void tegra_shared_plane_atomic_update(struct= drm_plane *plane, > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE); > =20 > if (yuv && planes > 1) { > - base =3D tegra_plane_state->iova[1] + fb->offsets[1]; > + uint8_t u =3D tegra_plane_state->swap_uv ? 2 : 1; > + uint8_t v =3D tegra_plane_state->swap_uv ? 1 : 2; > + > + base =3D tegra_plane_state->iova[u] + fb->offsets[u]; > base |=3D addr_flag; > =20 > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_U); > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_U); > =20 > if (planes > 2) { > - base =3D tegra_plane_state->iova[2] + fb->offsets[2]; > + base =3D tegra_plane_state->iova[v] + fb->offsets[v]; > base |=3D addr_flag; > =20 > tegra_plane_writel(p, upper_32_bits(base), DC_WINBUF_START_ADDR_HI_V)= ; > tegra_plane_writel(p, lower_32_bits(base), DC_WINBUF_START_ADDR_V); > } > =20 > - value =3D PITCH_U(fb->pitches[1]); > + value =3D PITCH_U(fb->pitches[u]); > =20 > if (planes > 2) > - value |=3D PITCH_V(fb->pitches[2]); > + value |=3D PITCH_V(fb->pitches[v]); > =20 > tegra_plane_writel(p, value, DC_WIN_PLANAR_STORAGE_UV); > } else { I noticed DC_WIN_PRECOMP_WGRP_PARAMS has a SWAP_UV bit. This is already=20 defined in dc.h. So we can use that for the hub.c implementation instead=20 of manually swapping. Otherwise everything looks good to me. We could also enable the swap_uv=20 logic for other UV formats. Cheers Mikko > diff --git a/drivers/gpu/drm/tegra/plane.c b/drivers/gpu/drm/tegra/plane.= c > index 2148b0c59815c..757bc552809fe 100644 > --- a/drivers/gpu/drm/tegra/plane.c > +++ b/drivers/gpu/drm/tegra/plane.c > @@ -59,6 +59,7 @@ tegra_plane_atomic_duplicate_state(struct drm_plane *pl= ane) > copy->tiling =3D state->tiling; > copy->format =3D state->format; > copy->swap =3D state->swap; > + copy->swap_uv =3D state->swap_uv; > copy->reflect_x =3D state->reflect_x; > copy->reflect_y =3D state->reflect_y; > copy->opaque =3D state->opaque; > @@ -319,11 +320,13 @@ int tegra_plane_state_add(struct tegra_plane *plane= , > return 0; > } > =20 > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap) > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv= ) > { > /* assume no swapping of fetched data */ > if (swap) > *swap =3D BYTE_SWAP_NOSWAP; > + if (swap_uv) > + *swap_uv =3D false; > =20 > switch (fourcc) { > case DRM_FORMAT_ARGB4444: > diff --git a/drivers/gpu/drm/tegra/plane.h b/drivers/gpu/drm/tegra/plane.= h > index e33a581e6490e..dba5f1b254e98 100644 > --- a/drivers/gpu/drm/tegra/plane.h > +++ b/drivers/gpu/drm/tegra/plane.h > @@ -49,6 +49,7 @@ struct tegra_plane_state { > struct tegra_bo_tiling tiling; > u32 format; > u32 swap; > + bool swap_uv; > =20 > bool reflect_x; > bool reflect_y; > @@ -88,7 +89,7 @@ void tegra_plane_cleanup_fb(struct drm_plane *plane, > int tegra_plane_state_add(struct tegra_plane *plane, > struct drm_plane_state *state); > =20 > -int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap); > +int tegra_plane_format(u32 fourcc, u32 *format, u32 *swap, bool *swap_uv= ); > bool tegra_plane_format_is_indexed(unsigned int format); > bool tegra_plane_format_is_yuv(unsigned int format, unsigned int *planes= , unsigned int *bpc); > int tegra_plane_setup_legacy_state(struct tegra_plane *tegra, >=20 > --=20 > 2.54.0 >=20 >=20 >=20