From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 26741C43219 for ; Tue, 18 Oct 2022 13:31:15 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229994AbiJRNbN (ORCPT ); Tue, 18 Oct 2022 09:31:13 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:36604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229509AbiJRNbL (ORCPT ); Tue, 18 Oct 2022 09:31:11 -0400 Received: from aposti.net (aposti.net [89.234.176.197]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E8D8C6945; Tue, 18 Oct 2022 06:31:09 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=crapouillou.net; s=mail; t=1666099867; h=from:from:sender:reply-to:subject:subject:date:date: message-id:message-id:to:to:cc:cc:mime-version:mime-version: content-type:content-type: content-transfer-encoding:content-transfer-encoding: in-reply-to:in-reply-to:references:references; bh=g3MzspTM9Dr8LSMMQ6MITd3EeKWr2rZaVT6P5JRlgFc=; b=nAc34R932407pmkTMuqbozzx64BjLHj4VBOG8Q9x82Nm0YPEk6WYI4Uvc+AY6jgKIlUogL scmhs6NBK2SX5jpT1AvnxBbIwdc6oZb0UK1wNsQDthGPSXu24u6WwISI01Lqur1NB8HcAd G5hGjtV2EBVWvTh2Fu7f5al1oI1Bf94= Date: Tue, 18 Oct 2022 14:30:57 +0100 From: Paul Cercueil Subject: Re: [PATCH v2 4/4] clk: Add Ingenic JZ4755 CGU driver To: Siarhei Volkau Cc: Michael Turquette , Stephen Boyd , Rob Herring , Krzysztof Kozlowski , Thomas Bogendoerfer , linux-clk@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-mips@vger.kernel.org Message-Id: In-Reply-To: References: <20221016150110.3020451-1-lis8215@gmail.com> <20221016150110.3020451-5-lis8215@gmail.com> <0S4WJR.4KB18PR21S9K1@crapouillou.net> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Siarhei, Le lun., oct. 17 2022 at 21:07:47 +0300, Siarhei Volkau=20 a =C3=A9crit : > =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 20:24, Paul Cerc= ueil=20 > : >>=20 >>=20 >>=20 >> Le lun., oct. 17 2022 at 20:10:56 +0300, Siarhei Volkau >> a =C3=A9crit : >> > =D0=BF=D0=BD, 17 =D0=BE=D0=BA=D1=82. 2022 =D0=B3. =D0=B2 12:24, Paul = Cercueil >> > : >> > >> >> > + [JZ4755_CLK_AIC] =3D { >> >> > + "aic", CGU_CLK_GATE, >> >> > + .parents =3D { JZ4755_CLK_I2S, -1, -1, -1 }, >> >> >> >> Wrong parent here, should be JZ4755_CLK_EXT_HALF. >> > >> > I don't agree, see Figure 20-13 in the JZ4755 PM. >>=20 >> 20-13 describes the I2S clock, no? >=20 > See 20.4.9 Serial Audio Clocks and Sampling Frequencies. > It stated that: "For internal CODEC ... CODEC needs a 12MHz > clock from CPM called SYS_CLK ...", but SYS_CLK is described > only in the I2S Controller section. I assume it is the same clock. Yes, and your SYS_CLK is the I2S clock, not the AIC clock. >>=20 >> AIC clock's parent is EXT/2 according to the diagram in 8.2.2. >>=20 >=20 > It's a bit cryptic manual, who knows how it's done in the HW. > I observed that codec runs on a desired sample rate only when PLL > equals 432 or 216 MHz, but SYS_CLK is definitely configured to be > 12MHz - from EXTCLK. On other PLL frequencies it is lower by > 2-4% than expected. That isn't observed on JZ4725B. The audio codec supplies SYS_CLK to the controller, not the other way=20 around. Parent the I2S clock to EXT/2 (which is 12 MHz) and it should=20 work fine, independently of the PLL. The AIC clock does not drive anything, it only "powers" the AIC module.=20 It should be parented only to EXT/2, similar to what's done in every=20 other CGU driver. Cheers, -Paul