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Wed, 4 Oct 2023 07:23:59 +0000 Received: from MA0P287MB0332.INDP287.PROD.OUTLOOK.COM ([fe80::efe9:8d54:281b:23f7]) by MA0P287MB0332.INDP287.PROD.OUTLOOK.COM ([fe80::efe9:8d54:281b:23f7%3]) with mapi id 15.20.6838.028; Wed, 4 Oct 2023 07:23:59 +0000 Message-ID: Date: Wed, 4 Oct 2023 15:23:54 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 4/5] riscv: dts: sophgo: add initial CV1800B SoC device tree To: Jisheng Zhang , Thomas Gleixner , Marc Zyngier , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Palmer Dabbelt , Paul Walmsley , Albert Ou , Daniel Lezcano , Anup Patel Cc: linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Inochi Amaoto , chao.wei@sophgo.com, xiaoguang.xing@sophgo.com References: <20230930123937.1551-1-jszhang@kernel.org> <20230930123937.1551-5-jszhang@kernel.org> From: Chen Wang In-Reply-To: <20230930123937.1551-5-jszhang@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-TMN: [es5SnY2jD3jNz/solUs2BPXbk+GIgyxJ] X-ClientProxiedBy: SI2PR02CA0040.apcprd02.prod.outlook.com (2603:1096:4:196::6) To MA0P287MB0332.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:ab::5) X-Microsoft-Original-Message-ID: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA0P287MB0332:EE_|PN3P287MB1848:EE_ X-MS-Office365-Filtering-Correlation-Id: 290731ac-6c5d-4ad5-c45c-08dbc4aae049 X-Microsoft-Antispam: BCL:0; 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To facilitate future management and review, I recommend registering the maintainer information in two entries in MAINTAINERS. The example is as follows: ``` SOPHGO CV180X DEVICETREES M:  Jisheng Zhang F:  arch/riscv/boot/dts/sophgo/cv1800b-milkv-duo.dts F:  arch/riscv/boot/dts/sophgo/cv1800b.dtsi SOPHGO SG2042 DEVICETREES M:  Chao Wei M:  Chen Wang S:  Maintained F:  arch/riscv/boot/dts/sophgo/Makefile F:  arch/riscv/boot/dts/sophgo/sg2042-cpus.dtsi F:  arch/riscv/boot/dts/sophgo/sg2042-milkv-pioneer.dts F:  arch/riscv/boot/dts/sophgo/sg2042.dtsi F:  Documentation/devicetree/bindings/riscv/sophgo.yaml ``` For Makefile and sophgo.yaml such common files, just keep in sg2042 entry should be fine. @Conor, what do you think? Thanks, Chen > diff --git a/arch/riscv/boot/dts/sophgo/cv1800b.dtsi b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > new file mode 100644 > index 000000000000..8829bebaa017 > --- /dev/null > +++ b/arch/riscv/boot/dts/sophgo/cv1800b.dtsi > @@ -0,0 +1,117 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2023 Jisheng Zhang > + */ > + > +#include > + > +/ { > + compatible = "sophgo,cv1800b"; > + #address-cells = <1>; > + #size-cells = <1>; > + > + cpus: cpus { > + #address-cells = <1>; > + #size-cells = <0>; > + timebase-frequency = <25000000>; > + > + cpu0: cpu@0 { > + compatible = "thead,c906", "riscv"; > + device_type = "cpu"; > + reg = <0>; > + d-cache-block-size = <64>; > + d-cache-sets = <512>; > + d-cache-size = <65536>; > + i-cache-block-size = <64>; > + i-cache-sets = <128>; > + i-cache-size = <32768>; > + mmu-type = "riscv,sv39"; > + riscv,isa = "rv64imafdc"; > + riscv,isa-base = "rv64i"; > + riscv,isa-extensions = "i", "m", "a", "f", "d", "c", "zicntr", "zicsr", > + "zifencei", "zihpm"; > + > + cpu0_intc: interrupt-controller { > + compatible = "riscv,cpu-intc"; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <1>; > + }; > + }; > + }; > + > + osc: oscillator { > + compatible = "fixed-clock"; > + clock-output-names = "osc_25m"; > + #clock-cells = <0>; > + }; > + > + soc { > + compatible = "simple-bus"; > + interrupt-parent = <&plic>; > + #address-cells = <1>; > + #size-cells = <1>; > + dma-noncoherent; > + ranges; > + > + uart0: serial@04140000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04140000 0x100>; > + interrupts = <44 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart1: serial@04150000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04150000 0x100>; > + interrupts = <45 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart2: serial@04160000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04160000 0x100>; > + interrupts = <46 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart3: serial@04170000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x04170000 0x100>; > + interrupts = <47 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + uart4: serial@041c0000 { > + compatible = "snps,dw-apb-uart"; > + reg = <0x041c0000 0x100>; > + interrupts = <48 IRQ_TYPE_LEVEL_HIGH>; > + clocks = <&osc>; > + reg-shift = <2>; > + reg-io-width = <4>; > + status = "disabled"; > + }; > + > + plic: interrupt-controller@70000000 { > + compatible = "sophgo,cv1800b-plic", "thead,c900-plic"; > + reg = <0x70000000 0x4000000>; > + interrupts-extended = <&cpu0_intc 11>, <&cpu0_intc 9>; > + interrupt-controller; > + #address-cells = <0>; > + #interrupt-cells = <2>; > + riscv,ndev = <101>; > + }; > + }; > +};