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Mon, 27 Nov 2023 08:07:14 +0000 Received: from MA0P287MB0332.INDP287.PROD.OUTLOOK.COM ([fe80::b1a7:eee7:e903:9ef3]) by MA0P287MB0332.INDP287.PROD.OUTLOOK.COM ([fe80::b1a7:eee7:e903:9ef3%7]) with mapi id 15.20.7025.022; Mon, 27 Nov 2023 08:07:14 +0000 Message-ID: Date: Mon, 27 Nov 2023 16:07:12 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 3/4] clk: sophgo: Add SG2042 clock generator driver To: Krzysztof Kozlowski , Chen Wang , aou@eecs.berkeley.edu, chao.wei@sophgo.com, conor@kernel.org, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com References: <81d421c8-bfd6-42b5-9da1-f067792f8f48@linaro.org> From: Chen Wang In-Reply-To: <81d421c8-bfd6-42b5-9da1-f067792f8f48@linaro.org> Content-Type: text/plain; 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>> + int i, ret = 0; >> + int num_clks = 0; >> + >> + num_clks = ARRAY_SIZE(sg2042_pll_clks) + >> + ARRAY_SIZE(sg2042_div_clks) + >> + ARRAY_SIZE(sg2042_gate_clks) + >> + ARRAY_SIZE(sg2042_mux_clks); >> + if (num_clks == 0) { >> + ret = -EINVAL; >> + goto error_out; >> + } >> + >> + ret = sg2042_clk_init_clk_data(node, num_clks, &clk_data); >> + if (ret < 0) >> + goto error_out; >> + >> + ret = sg2042_clk_register_plls(clk_data, sg2042_pll_clks, >> + ARRAY_SIZE(sg2042_pll_clks)); >> + if (ret) >> + goto cleanup; >> + >> + ret = sg2042_clk_register_divs(clk_data, sg2042_div_clks, >> + ARRAY_SIZE(sg2042_div_clks)); >> + if (ret) >> + goto cleanup; >> + >> + ret = sg2042_clk_register_gates(clk_data, sg2042_gate_clks, >> + ARRAY_SIZE(sg2042_gate_clks)); >> + if (ret) >> + goto cleanup; >> + >> + ret = sg2042_clk_register_muxs(clk_data, sg2042_mux_clks, >> + ARRAY_SIZE(sg2042_mux_clks)); >> + if (ret) >> + goto cleanup; >> + >> + for (i = 0; i < num_clks; i++) >> + dbg_info("provider [%d]: %s\n", i, clk_hw_get_name(clk_data->onecell_data.hws[i])); >> + ret = of_clk_add_hw_provider(node, of_clk_hw_onecell_get, &clk_data->onecell_data); >> + if (ret) >> + goto cleanup; >> + >> + return; >> + >> +cleanup: >> + for (i = 0; i < num_clks; i++) { >> + if (clk_data->onecell_data.hws[i] != NULL) >> + clk_hw_unregister(clk_data->onecell_data.hws[i]); >> + } >> + kfree(clk_data); >> + >> +error_out: >> + pr_err("%s failed error number %d\n", __func__, ret); >> +} >> + >> +CLK_OF_DECLARE(sg2042_clk, "sophgo,sg2042-clkgen", sg2042_clk_init); > No, this should be platform device. It's a child of another device, so > you cannot use other way of init ordering. hi, Krzysztof, Thanks for your review. I don't quite understand your opinion. Do you mean CLK_OF_DECLARE is only used for platform device so it can not be use here? But I think this driver is still for platform device though I move the clock controller node as a child of the system contoller node. System controller node is just a block of registers which are used to control some other platform devices ,such as clock controller, reset controller and pin controller for this SoC. And I also see other similar code in kernel, for example: drivers/clk/clk-k210.c. And I'm confused by your input "so you cannot use other way of init ordering." Do you mean "so you CAN use other way of init ordering"? What's the other way of init ordering do you mean? Thanks, Chen