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Fri, 12 Jan 2024 08:35:11 +0000 Received: from MA0P287MB2822.INDP287.PROD.OUTLOOK.COM ([fe80::6e80:69e1:f2e7:d70d]) by MA0P287MB2822.INDP287.PROD.OUTLOOK.COM ([fe80::6e80:69e1:f2e7:d70d%3]) with mapi id 15.20.7181.020; Fri, 12 Jan 2024 08:35:11 +0000 Message-ID: Date: Fri, 12 Jan 2024 16:35:08 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v7 2/4] dt-bindings: clock: sophgo: support SG2042 To: Conor Dooley , Krzysztof Kozlowski Cc: Conor Dooley , Krzysztof Kozlowski , Chen Wang , aou@eecs.berkeley.edu, chao.wei@sophgo.com, krzysztof.kozlowski+dt@linaro.org, mturquette@baylibre.com, palmer@dabbelt.com, paul.walmsley@sifive.com, richardcochran@gmail.com, robh+dt@kernel.org, sboyd@kernel.org, devicetree@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, haijiao.liu@sophgo.com, xiaoguang.xing@sophgo.com, guoren@kernel.org, jszhang@kernel.org, inochiama@outlook.com, samuel.holland@sifive.com References: <925d99d5b4ece01337cb3389aaea4b631894dd1d.1704694903.git.unicorn_wang@outlook.com> <20240110-untoasted-underfed-fe81479506f6@spud> <20240111-jolly-prize-930931cc648a@spud> <20240112-overhead-disallow-8c2a4b97c36c@wendy> From: Chen Wang In-Reply-To: <20240112-overhead-disallow-8c2a4b97c36c@wendy> Content-Type: text/plain; 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On 2024/1/12 15:42, Conor Dooley wrote: > On Fri, Jan 12, 2024 at 08:08:15AM +0800, Chen Wang wrote: >> On 2024/1/12 0:58, Conor Dooley wrote: >>> On Thu, Jan 11, 2024 at 04:00:04PM +0800, Chen Wang wrote: >>>> There are four types of clocks for SG2042 and following are where their >>>> control registers are defined in: >>>> >>>> PLL：all in SYS_CTRL >>>> DIV: all in CLOCK >>>> GATE: some are in SYS_CTRL, some others are in CLOCK >>> When you say "some", do you meant some entire clocks are in SYS_CTRL and >>> some entire clocks are in the CLOCKS? Or do you meant that for a given >>> clock, some registers are in SYS_CTRL and some are in CLOCK? It's the >>> first option, right? >> It's the first option. > Then the gate clocks that are fully contained within SYS_CTRL are > outputs of SYS_CTRL and gate clocks fully contained within CLOCK are > outputs of CLOCK. You should not use a phandle to SYS_CTRL from the > CLOCKS node so that you can pretend they are part of CLOCKS just because > that makes writing your driver easier. That said, obviously you can > share the routines for turning the gates on and off etc. > > Cheers, > Conor.