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Fri, 12 Jul 2024 01:33:53 +0000 Received: from MA0P287MB2822.INDP287.PROD.OUTLOOK.COM ([fe80::a94:ad0a:9071:806c]) by MA0P287MB2822.INDP287.PROD.OUTLOOK.COM ([fe80::a94:ad0a:9071:806c%5]) with mapi id 15.20.7762.020; Fri, 12 Jul 2024 01:33:52 +0000 Message-ID: Date: Fri, 12 Jul 2024 09:33:46 +0800 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 0/4] Add board support for Sipeed LicheeRV Nano To: Thomas Bonnefille , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Inochi Amaoto , Chao Wei , Conor Dooley Cc: Albert Ou , Palmer Dabbelt , Samuel Holland , Thomas Gleixner , Daniel Lezcano , Thomas Petazzoni , =?UTF-8?Q?Miqu=C3=A8l_Raynal?= , linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, Conor Dooley References: <20240711-sg2002-v4-0-d97ec2367095@bootlin.com> From: Chen Wang In-Reply-To: <20240711-sg2002-v4-0-d97ec2367095@bootlin.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-TMN: [XLMLPywzSoIB5ldrPMmiF5rG5qJ0wW4h] X-ClientProxiedBy: SI2PR02CA0017.apcprd02.prod.outlook.com (2603:1096:4:194::17) To MA0P287MB2822.INDP287.PROD.OUTLOOK.COM (2603:1096:a01:138::5) X-Microsoft-Original-Message-ID: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA0P287MB2822:EE_|PN0P287MB0489:EE_ X-MS-Office365-Filtering-Correlation-Id: 4d173977-b2dc-46f9-41ab-08dca212afeb X-Microsoft-Antispam: BCL:0;ARA:14566002|19110799003|8060799006|461199028|4302099013|3412199025|440099028|1602099012; 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Because they are all related to sophgo, it would be better to PR them together to avoid confusion. Especially about the change of sifive,plic-1.0.0.yaml, my original understanding was that it should be handled by you. Regards, Chen On 2024/7/11 18:01, Thomas Bonnefille wrote: > The LicheeRV Nano is a RISC-V SBC based on the Sophgo SG2002 chip. Adds > minimal device tree files for this board to make it boot to a basic > shell. > > Signed-off-by: Thomas Bonnefille > --- > Changes in v4: > - Add correct bindings configuration for SG2002 sdhci > - Drop commit "dt-bindings: timer: Add SOPHGO SG2002 clint" because it > has already been merged in Daniel Lezcano git tree. > - Link to v3: https://lore.kernel.org/r/20240709-sg2002-v3-0-af779c3d139d@bootlin.com > > Changes in v3: > - Remove /dts-v1/ directive from sg2002.dtsi file > - Add disable-wp property to sdhci node to avoid having a write > protected SD card > - Drop changes in cv18xx.dtsi and cv1800b.dtsi > - Add fallback compatible to cv1800b in SDHCI node of sg2002.dtsi > - Link to v2: https://lore.kernel.org/r/20240612-sg2002-v2-0-19a585af6846@bootlin.com > > Changes in v2: > - Add SDHCI support > - Change device tree name to match the Makefile > - Add oscillator frequency > - Add aliases to other UARTs > - Add aliases to GPIOs > - Move compatible for SDHCI from common DT to specific DT > - Link to v1: https://lore.kernel.org/r/20240527-sg2002-v1-0-1b6cb38ce8f4@bootlin.com > > --- > Thomas Bonnefille (4): > dt-bindings: interrupt-controller: Add SOPHGO SG2002 plic > dt-bindings: riscv: Add Sipeed LicheeRV Nano board compatibles > riscv: dts: sophgo: Add initial SG2002 SoC device tree > riscv: dts: sophgo: Add LicheeRV Nano board device tree > > .../interrupt-controller/sifive,plic-1.0.0.yaml | 1 + > .../devicetree/bindings/riscv/sophgo.yaml | 5 ++ > arch/riscv/boot/dts/sophgo/Makefile | 1 + > .../boot/dts/sophgo/sg2002-licheerv-nano-b.dts | 54 ++++++++++++++++++++++ > arch/riscv/boot/dts/sophgo/sg2002.dtsi | 32 +++++++++++++ > 5 files changed, 93 insertions(+) > --- > base-commit: d20f6b3d747c36889b7ce75ee369182af3decb6b > change-id: 20240515-sg2002-93dce1d263be > > Best regards,