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X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MAUPR01MB13345 On 4/8/2026 12:01 AM, Icenowy Zheng wrote: > The SG2042 MSI controller has one 32-bit doorbell register, and each bit > corresponds to an interrupt. At a glance, it seems that the MSI > controller can support 32 interrupts; however the PCI MSI capability > only supports 16-bit messages, which makes the high 16 interrupts > unusable in such way. > > Reduce the MSI count to 16 to prevent producing MSI message values that > cannot fit 16-bit integers. > > Signed-off-by: Icenowy Zheng > --- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index 9fddf3f0b3b99..9f1820a7b5a9f 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -234,7 +234,7 @@ msi: msi-controller@7030010304 { > reg-names = "clr", "doorbell"; > msi-controller; > #msi-cells = <0>; > - msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 32>; > + msi-ranges = <&intc 64 IRQ_TYPE_EDGE_RISING 16>; > }; > > rpgate: clock-controller@7030010368 { LGTM. Reviewed-by: Chen Wang Tested-by: Chen Wang on Pioneerbox. Thanks, Chen Hi, Han, Will you please run some quick test on EVB boards, I have no such hardware in hand, thanks.