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2042 PCIe Root Ports To: Yao Zi , Manivannan Sadhasivam Cc: Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Rob Herring , Bjorn Helgaas , Siddharth Vadapalli , Hans Zhang <18255117159@163.com>, Kishon Vijay Abraham I , Manikandan K Pillai , Christophe JAILLET , Inochi Amaoto , Han Gao , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org References: <20260227181925.52475-1-me@ziyao.cc> <20260227181925.52475-3-me@ziyao.cc> From: Chen Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SG2PR03CA0085.apcprd03.prod.outlook.com (2603:1096:4:7c::13) To MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:1e9::18) X-Microsoft-Original-Message-ID: <5d268df0-1d7f-4771-9b37-352b9c053889@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email 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MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2026 12:26:48.2187 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MAXPR01MB4327 On 3/27/2026 4:19 PM, Yao Zi wrote: > On Thu, Mar 26, 2026 at 10:15:16PM +0530, Manivannan Sadhasivam wrote: >> On Fri, Feb 27, 2026 at 06:19:25PM +0000, Yao Zi wrote: >>> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM >>> states for devicetree platforms") force enable ASPM on all device tree >>> platform, the SG2042 root port breaks as it advertises L0s and L1 >>> capabilities without supporting it. >>> >>> Provide a platform-specific initialization hook to override the L0s and >>> L1 support advertised in LNKCAP register of SG2042 Root Ports, so it >>> doesn't try to enable those states. >>> >>> Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") >>> Co-authored-by: Inochi Amaoto >>> Signed-off-by: Inochi Amaoto >>> Signed-off-by: Yao Zi >>> --- >>> drivers/pci/controller/cadence/pcie-sg2042.c | 20 ++++++++++++++++++++ >>> 1 file changed, 20 insertions(+) >>> >>> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c >>> index 0c50c74d03ee..3142f82bd393 100644 >>> --- a/drivers/pci/controller/cadence/pcie-sg2042.c >>> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c >>> @@ -32,6 +32,25 @@ static struct pci_ops sg2042_pcie_child_ops = { >>> .write = pci_generic_config_write, >>> }; >>> >>> +static int sg2042_pcie_disable_l0s_l1(struct cdns_pcie_rc *rc) >>> +{ >>> + struct cdns_pcie *pcie = &rc->pcie; >>> + u32 pcie_lnkcap_off; >>> + u32 lnkcap; >>> + >>> + pcie_lnkcap_off = CDNS_PCIE_RP_CAP_OFFSET + PCI_EXP_LNKCAP; >>> + >>> + lnkcap = cdns_pcie_rp_readw(pcie, pcie_lnkcap_off); >>> + lnkcap &= ~PCI_EXP_LNKCAP_ASPMS; >>> + cdns_pcie_rp_writew(pcie, pcie_lnkcap_off, lnkcap); >>> + >> cadence-host driver already has cdns_pcie_host_init_root_port() to initialize >> the Root Port. Since your intention is to modify the LNKCAP field, which belongs >> to the Root Port, you should do that in cdns_pcie_host_init_root_port() instead. >> I see no sg2042 specific registers used in this patch, so just set a flag in >> this driver like 'broken_aspm' and clear PCI_EXP_LNKCAP_ASPMS if set in >> cdns_pcie_host_init_root_port(). > Okay, it makes sense. Will do it in v3. Keep it up, Yao :) I'm looking forward to your v3! Chen >> - Mani >> >> -- >> மணிவண்ணன் சதாசிவம் > Regards, > Yao Zi