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SG2042 PCIe controllers To: Han Gao , Bjorn Helgaas , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Inochi Amaoto , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Zixian Zeng Cc: linux-pci@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Han Gao , stable@vger.kernel.org References: <20260331171248.973014-1-gaohan@iscas.ac.cn> <20260331171248.973014-3-gaohan@iscas.ac.cn> From: Chen Wang In-Reply-To: <20260331171248.973014-3-gaohan@iscas.ac.cn> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TP0P295CA0015.TWNP295.PROD.OUTLOOK.COM (2603:1096:910:2::13) To MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:1e9::18) X-Microsoft-Original-Message-ID: <25947a4c-b000-4548-810b-60dc4572713a@outlook.com> Precedence: bulk X-Mailing-List: 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c5c54316-acdd-492e-5758-08de9093ff7e X-MS-Exchange-CrossTenant-AuthSource: MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 02 Apr 2026 08:44:05.6430 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PN0PR01MB9119 On 4/1/2026 1:12 AM, Han Gao wrote: > SG2042's PCIe root complexes are cache-coherent with the CPU. Mark all > four PCIe controller nodes (pcie_rc0 through pcie_rc3) as dma-coherent > so the kernel uses coherent DMA mappings instead of non-coherent bounce > buffering. > > Cc: stable@vger.kernel.org > Signed-off-by: Han Gao > --- > arch/riscv/boot/dts/sophgo/sg2042.dtsi | 4 ++++ > 1 file changed, 4 insertions(+) > > diff --git a/arch/riscv/boot/dts/sophgo/sg2042.dtsi b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > index 9fddf3f0b3b9..3af770549742 100644 > --- a/arch/riscv/boot/dts/sophgo/sg2042.dtsi > +++ b/arch/riscv/boot/dts/sophgo/sg2042.dtsi > @@ -417,6 +417,7 @@ pcie_rc0: pcie@7060000000 { > vendor-id = <0x1f1c>; > device-id = <0x2042>; > cdns,no-bar-match-nbits = <48>; > + dma-coherent; > msi-parent = <&msi>; > status = "disabled"; > }; > @@ -439,6 +440,7 @@ pcie_rc1: pcie@7060800000 { > vendor-id = <0x1f1c>; > device-id = <0x2042>; > cdns,no-bar-match-nbits = <48>; > + dma-coherent; > msi-parent = <&msi>; > status = "disabled"; > }; > @@ -461,6 +463,7 @@ pcie_rc2: pcie@7062000000 { > vendor-id = <0x1f1c>; > device-id = <0x2042>; > cdns,no-bar-match-nbits = <48>; > + dma-coherent; > msi-parent = <&msi>; > status = "disabled"; > }; > @@ -483,6 +486,7 @@ pcie_rc3: pcie@7062800000 { > vendor-id = <0x1f1c>; > device-id = <0x2042>; > cdns,no-bar-match-nbits = <48>; > + dma-coherent; > msi-parent = <&msi>; > status = "disabled"; > }; For binding changes, LGTM. But I have a question regarding this change in dtsi. From your patch description, I understand that enabling the `dma-coherent` attribute requires upgrading the firmware `fip.bin`. If a user only updates the kernel (which is relatively easy) but forgets or doesn't know how to upgrade the firmware, enabling `coherent` might cause the kernel to skip all explicit cache maintenance operations. Could this pose a subtle risk? Wouldn't it be safer to leave the upstream unchanged in dtsi and allow users to add the `dma-coherent` attribute themselves after they upgrade the firmware? I would greatly appreciate your guidance. Thanks, Chen