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2042/2044 PCIe Root Ports To: Bjorn Helgaas , Inochi Amaoto Cc: Bjorn Helgaas , Han Gao , Manivannan Sadhasivam , linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Yixun Lan , Longbin Li References: <20251226163031.GA4128882@bhelgaas> From: Chen Wang In-Reply-To: <20251226163031.GA4128882@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: TYCP286CA0171.JPNP286.PROD.OUTLOOK.COM (2603:1096:400:3c6::6) To MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:1e9::18) X-Microsoft-Original-Message-ID: <310493fd-dc20-4530-bc2f-0cecb9ec22e0@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-MessageSentRepresentingType: 1 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: MA5PR01MB12500:EE_|MA5PR01MB11147:EE_ X-MS-Office365-Filtering-Correlation-Id: a7d09311-fb16-4447-1a77-08de466faffa X-Microsoft-Antispam: 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=?utf-8?B?WW8rNElrOEU2QmtsVTc4NXBSVmlMM0NaR2FPbmtUblNzMkw3dFZlY3k3U0Uy?= =?utf-8?Q?Y7ya5bGE0QdsFHGjggj4/e+7t/qnKQFD?= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: a7d09311-fb16-4447-1a77-08de466faffa X-MS-Exchange-CrossTenant-AuthSource: MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Dec 2025 00:17:46.1925 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA5PR01MB11147 On 12/27/2025 12:30 AM, Bjorn Helgaas wrote: > On Thu, Dec 25, 2025 at 06:05:27PM +0800, Inochi Amaoto wrote: >> Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM >> states for devicetree platforms") force enable ASPM on all device tree >> platform, the SG2042/SG2044 PCIe Root Ports breaks as it advertises L0s >> and L1 capabilities without supporting it. >> >> Override the L0s and L1 Support advertised in Link Capabilities by the >> SG2042/SG2044 Root Ports so we don't try to enable those states. >> >> Inochi Amaoto (2): >> PCI/ASPM: Avoid L0s and L1 on Sophgo 2042 PCIe [1f1c:2042] Root Ports >> PCI/ASPM: Avoid L0s and L1 on Sophgo 2044 PCIe [1f1c:2044] Root Ports >> >> drivers/pci/quirks.c | 2 ++ >> include/linux/pci_ids.h | 2 ++ >> 2 files changed, 4 insertions(+) > 1) Can somebody at Sophgo confirm that this is a hardware erratum? I > just want to make rule out some kind of OS bug in configuring L0s/L1. > > 2) Why don't we have a MAINTAINERS entry for this driver? I failed to > notice that the series we applied > (https://lore.kernel.org/all/cover.1757643388.git.unicorn_wang@outlook.com/) > does not include a maintainer. Chen, since you posted that series, > are you willing to sign up to maintain it? Sorry, I didn't realize I needed to submit maintainer information separately for each driver when I submitted the PCIe driver code. Yes, I will be maintaining the SG2042 PCIe driver. Do I need to add an entry to the MAINTAINERS file? Chen > > Bjorn