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Sophgo 2042 PCIe Root Ports To: Yao Zi , Lorenzo Pieralisi , =?UTF-8?Q?Krzysztof_Wilczy=C5=84ski?= , Manivannan Sadhasivam , Rob Herring , Bjorn Helgaas , Siddharth Vadapalli , Hans Zhang <18255117159@163.com>, Kishon Vijay Abraham I , Manikandan K Pillai , Christophe JAILLET , Inochi Amaoto , Han Gao Cc: linux-pci@vger.kernel.org, linux-kernel@vger.kernel.org, Han Gao References: <20260405154154.46829-1-me@ziyao.cc> <20260405154154.46829-3-me@ziyao.cc> From: Chen Wang In-Reply-To: <20260405154154.46829-3-me@ziyao.cc> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SI2PR01CA0042.apcprd01.prod.exchangelabs.com (2603:1096:4:193::23) To MA5PR01MB12500.INDPRD01.PROD.OUTLOOK.COM (2603:1096:a01:1e9::18) X-Microsoft-Original-Message-ID: <1ab3df95-f17d-4328-a956-fb6981708614@outlook.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 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08:24:10.5527 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PN0PR01MB8944 On 4/5/2026 11:41 PM, Yao Zi wrote: > Since commit f3ac2ff14834 ("PCI/ASPM: Enable all ClockPM and ASPM > states for devicetree platforms") force enable ASPM on all device tree > platform, the SG2042 root port breaks as it advertises L0s and L1 > capabilities without supporting it. > > Set ASPM quirks to disable advertisement of L0s and L1 support, so > it doesn't try to enable those states. > > Fixes: 4e27aca4881a ("riscv: sophgo: dts: add PCIe controllers for SG2042") > Co-developed-by: Inochi Amaoto > Signed-off-by: Inochi Amaoto > Signed-off-by: Yao Zi > Tested-by: Han Gao > --- > drivers/pci/controller/cadence/pcie-sg2042.c | 2 ++ > 1 file changed, 2 insertions(+) > > diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c > index 0c50c74d03ee..4a2af4d0713e 100644 > --- a/drivers/pci/controller/cadence/pcie-sg2042.c > +++ b/drivers/pci/controller/cadence/pcie-sg2042.c > @@ -48,6 +48,8 @@ static int sg2042_pcie_probe(struct platform_device *pdev) > bridge->child_ops = &sg2042_pcie_child_ops; > > rc = pci_host_bridge_priv(bridge); > + rc->quirk_broken_aspm_l0s = 1; > + rc->quirk_broken_aspm_l1 = 1; > pcie = &rc->pcie; > pcie->dev = dev; > LGTM. Reviewed-by: Chen Wang Tested-by: Chen Wang on Pioneerbox. Thanks, Chen