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driver To: Bjorn Helgaas , Chen Wang Cc: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com References: <20250910143453.GA1533730@bhelgaas> From: Chen Wang In-Reply-To: <20250910143453.GA1533730@bhelgaas> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-ClientProxiedBy: SG2PR02CA0001.apcprd02.prod.outlook.com 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=?utf-8?B?Q1MzdUJmRTk2d0M3SHZHdStLUVpnSzAyMUhOVCthK3hEbjdYQ3JHeDdRYVl5?= =?utf-8?B?aFppNG5YNzlPbUtuZVpMTHEvL0xIUXdzZjBwRDRCSjJORFRRR3JTL1FjbDlH?= =?utf-8?B?aDBtakxPbTVCeGc3SU9HU1hFbGY1NUY4cGhUNGlnVlFhVThaSlc4cTdpNWFH?= =?utf-8?Q?ynFRqVQbMMIc4ouUxFOBewblGKOEof+5WCkneHe?= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: e497483c-f6e8-4d87-4881-08ddf0c77b53 X-MS-Exchange-CrossTenant-AuthSource: MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 11 Sep 2025 00:09:31.7972 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PNZPR01MB4125 On 9/10/2025 10:34 PM, Bjorn Helgaas wrote: > On Wed, Sep 10, 2025 at 10:08:39AM +0800, Chen Wang wrote: >> From: Chen Wang >> >> Add support for PCIe controller in SG2042 SoC. The controller >> uses the Cadence PCIe core programmed by pcie-cadence*.c. The >> PCIe controller will work in host mode only, supporting data >> rate(gen4) and lanes(x16 or x8). > Strictly speaking, "gen4" is a spec revision, not a data rate. > Include the GT/s rate instead or in addition. We can fix this when > merging if there's no other reason to repost (I assume you mean 16 > GT/s). Will also add spaces before the open "(". Yes, I meant 16 GT/s. Please help fix this when merging together with dropping period at end of subject for the [2/7], if no repost. Thanks, Chen