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driver To: Manivannan Sadhasivam , Chen Wang Cc: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com References: <1df25b33f0ea90a81c34c18cadedd38526a30f01.1756344464.git.unicorn_wang@outlook.com> From: Chen Wang In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit X-ClientProxiedBy: SI2PR01CA0052.apcprd01.prod.exchangelabs.com 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=?utf-8?B?R3NOVmxqWUZjRDB4aitkcTQvdTZxQ2RXWkRKcVh4MUdoMzlKYnRBZUdJcXJM?= =?utf-8?B?L1F5SGEwQktsT0xZV0dIOE02TUlGeXBKNkNEOWE2K0xycG9tSTNvcDNsM2di?= =?utf-8?B?N0UzRHZaekNRZzNDc2p3cWxCbVl2d2J0Tm9mVnhWWFd3K0JmREVJTjVtRlcz?= =?utf-8?Q?0SyzCYUJeI4xqJwvjkiimzjuvDtrN1iS1abUbDy?= X-OriginatorOrg: outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 1ed304a2-86f1-45b2-8fe4-08dde91cde0e X-MS-Exchange-CrossTenant-AuthSource: MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 01 Sep 2025 06:00:35.5151 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 84df9e7f-e9f6-40af-b435-aaaaaaaaaaaa X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: PNZPR01MB4480 On 8/31/2025 12:45 PM, Manivannan Sadhasivam wrote: > On Thu, Aug 28, 2025 at 10:17:40AM GMT, Chen Wang wrote: >> From: Chen Wang >> >> Add support for PCIe controller in SG2042 SoC. The controller >> uses the Cadence PCIe core programmed by pcie-cadence*.c. The >> PCIe controller will work in host mode only. >> > Supported data rate, lanes etc... OK, I will add these descriptions in next revision. >> Signed-off-by: Chen Wang >> --- >> drivers/pci/controller/cadence/Kconfig | 12 ++ >> drivers/pci/controller/cadence/Makefile | 1 + >> drivers/pci/controller/cadence/pcie-sg2042.c | 134 +++++++++++++++++++ >> 3 files changed, 147 insertions(+) >> create mode 100644 drivers/pci/controller/cadence/pcie-sg2042.c >> >> diff --git a/drivers/pci/controller/cadence/Kconfig b/drivers/pci/controller/cadence/Kconfig >> index 666e16b6367f..b1f1941d5208 100644 >> --- a/drivers/pci/controller/cadence/Kconfig >> +++ b/drivers/pci/controller/cadence/Kconfig >> @@ -42,6 +42,17 @@ config PCIE_CADENCE_PLAT_EP >> endpoint mode. This PCIe controller may be embedded into many >> different vendors SoCs. >> >> +config PCIE_SG2042 > PCIE_SG2042_HOST ok > >> + bool "Sophgo SG2042 PCIe controller (host mode)" > Since this driver doesn't implement irqchip, you should make it tristate and as > a module. Yes, I will implement it as a module. > >> + depends on ARCH_SOPHGO || COMPILE_TEST >> + depends on OF > depends on OF && (ARCH_SOPHGO || COMPILE_TEST) OK [......] >> + >> + bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); >> + if (!bridge) { >> + dev_err(dev, "Failed to alloc host bridge!\n"); > Use dev_err_probe() here and below. OK >> + return -ENOMEM; >> + } >> + >> + bridge->ops = &sg2042_pcie_host_ops; >> + >> + rc = pci_host_bridge_priv(bridge); >> + pcie = &rc->pcie; > You are setting drvdata only below. Sorry, I don't understand your question here. I guess you are confused about the statement `platform_set_drvdata(pdev, pcie);`. Let me explain why we need to do like this. Originally, I defined a drvdata stucture: struct sg2042_pcie {     struct cdns_pcie    *cdns_pcie;     // other properties }; But after code cleanup, I find there is only "cdns_pcie" left, so I remove the `struct sg2042_pcie` and directy set `cdns_pcie` (in new version, it is renamed to pcie) as drvdata. >> + pcie->dev = dev; >> + >> + platform_set_drvdata(pdev, pcie); >> + >> + pm_runtime_enable(dev); >> + >> + ret = pm_runtime_get_sync(dev); >> + if (ret < 0) { >> + dev_err(dev, "pm_runtime_get_sync failed\n"); >> + goto err_get_sync; >> + } >> + > Why do you need pm_runtime_get_sync()? DT binding doesn't provide a > power-domain, so you just need: > > pm_runtime_set_active() > pm_runtime_no_callbacks() > devm_pm_runtime_enable() OK, I will improve this. >> + ret = cdns_pcie_init_phy(dev, pcie); >> + if (ret) { >> + dev_err(dev, "Failed to init phy!\n"); >> + goto err_get_sync; >> + } >> + >> + ret = cdns_pcie_host_setup(rc); >> + if (ret < 0) { >> + dev_err(dev, "Failed to setup host!\n"); >> + goto err_host_setup; >> + } >> + >> + return 0; >> + >> +err_host_setup: >> + cdns_pcie_disable_phy(pcie); >> + >> +err_get_sync: >> + pm_runtime_put(dev); >> + pm_runtime_disable(dev); >> + >> + return ret; >> +} >> + >> +static void sg2042_pcie_shutdown(struct platform_device *pdev) >> +{ >> + struct cdns_pcie *pcie = platform_get_drvdata(pdev); >> + struct device *dev = &pdev->dev; >> + >> + cdns_pcie_disable_phy(pcie); >> + >> + pm_runtime_put(dev); >> + pm_runtime_disable(dev); > You don't need these as per my above suggestion. OK. >> +} >> + >> +static const struct of_device_id sg2042_pcie_of_match[] = { >> + { .compatible = "sophgo,sg2042-pcie-host" }, >> + {}, >> +}; >> + >> +static struct platform_driver sg2042_pcie_driver = { >> + .driver = { >> + .name = "sg2042-pcie", >> + .of_match_table = sg2042_pcie_of_match, >> + .pm = &cdns_pcie_pm_ops, >> + }, >> + .probe = sg2042_pcie_probe, > Why no remove()? OK, I will replace shutdown with remove when I implement it as a module in next revision. Thanks, Chen > > - Mani >