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driver To: Rob Herring , Chen Wang Cc: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com References: <1df25b33f0ea90a81c34c18cadedd38526a30f01.1756344464.git.unicorn_wang@outlook.com> <20250829170908.GA1016165-robh@kernel.org> From: Chen Wang In-Reply-To: <20250829170908.GA1016165-robh@kernel.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 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1:09 AM, Rob Herring wrote: > On Thu, Aug 28, 2025 at 10:17:40AM +0800, Chen Wang wrote: [......] >> diff --git a/drivers/pci/controller/cadence/pcie-sg2042.c b/drivers/pci/controller/cadence/pcie-sg2042.c >> new file mode 100644 >> index 000000000000..fe434dc2967e >> --- /dev/null >> +++ b/drivers/pci/controller/cadence/pcie-sg2042.c >> @@ -0,0 +1,134 @@ >> +// SPDX-License-Identifier: GPL-2.0 >> +/* >> + * pcie-sg2042 - PCIe controller driver for Sophgo SG2042 SoC >> + * >> + * Copyright (C) 2025 Sophgo Technology Inc. >> + * Copyright (C) 2025 Chen Wang >> + */ >> + >> +#include >> +#include > Looks like you just need mod_devicetable.h instead. Thanks, I tried and seems just mod_devicetable.h does work. To be honest, I am more curious about how to know which header files should be included. Is it just based on experience, because sometimes including these or those header files will compile without any problems. >> +#include >> +#include >> +#include >> + >> +#include "pcie-cadence.h" >> + >> +/* >> + * SG2042 only support 4-byte aligned access, so for the rootbus (i.e. to read >> + * the Root Port itself, read32 is required. For non-rootbus (i.e. to read >> + * the PCIe peripheral registers, supports 1/2/4 byte aligned access, so >> + * directly using read should be fine. >> + * >> + * The same is true for write. >> + */ >> +static int sg2042_pcie_config_read(struct pci_bus *bus, unsigned int devfn, >> + int where, int size, u32 *value) >> +{ >> + if (pci_is_root_bus(bus)) > You can have separate pci_ops for the root bus and child buses. Do that > and then sg2042_pcie_config_read() goes away. IIRC, there's examples in > the tree of your exact issue (root bus being 32-bit only). Yes, you're right, I learned it. Thanks, >> + return pci_generic_config_read32(bus, devfn, where, size, >> + value); >> + >> + return pci_generic_config_read(bus, devfn, where, size, value); >> +} >> + >> +static int sg2042_pcie_config_write(struct pci_bus *bus, unsigned int devfn, >> + int where, int size, u32 value) >> +{ >> + if (pci_is_root_bus(bus)) >> + return pci_generic_config_write32(bus, devfn, where, size, >> + value); >> + >> + return pci_generic_config_write(bus, devfn, where, size, value); >> +} >> + >> +static struct pci_ops sg2042_pcie_host_ops = { >> + .map_bus = cdns_pci_map_bus, >> + .read = sg2042_pcie_config_read, >> + .write = sg2042_pcie_config_write, >> +}; >> + [......] >> + >> +static struct platform_driver sg2042_pcie_driver = { >> + .driver = { >> + .name = "sg2042-pcie", >> + .of_match_table = sg2042_pcie_of_match, >> + .pm = &cdns_pcie_pm_ops, >> + }, >> + .probe = sg2042_pcie_probe, >> + .shutdown = sg2042_pcie_shutdown, >> +}; >> +builtin_platform_driver(sg2042_pcie_driver); > What prevents this from being a module? Well, I'll check again. Thanks. Chen > Rob >