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driver To: ALOK TIWARI , Chen Wang , kwilczynski@kernel.org, u.kleine-koenig@baylibre.com, aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de, bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org, 18255117159@163.com, inochiama@gmail.com, kishon@kernel.org, krzk+dt@kernel.org, lpieralisi@kernel.org, mani@kernel.org, palmer@dabbelt.com, paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com, tglx@linutronix.de, thomas.richard@bootlin.com, sycamoremoon376@gmail.com, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, linux-riscv@lists.infradead.org, sophgo@lists.linux.dev, rabenda.cn@gmail.com, chao.wei@sophgo.com, xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com References: <1df25b33f0ea90a81c34c18cadedd38526a30f01.1756344464.git.unicorn_wang@outlook.com> <08d79767-4b9b-41c3-8d51-5ff879eacb31@oracle.com> From: Chen Wang In-Reply-To: <08d79767-4b9b-41c3-8d51-5ff879eacb31@oracle.com> Content-Type: text/plain; charset=UTF-8; format=flowed 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X-MS-Exchange-CrossTenant-RMS-PersistedConsumerOrg: 00000000-0000-0000-0000-000000000000 X-MS-Exchange-Transport-CrossTenantHeadersStamped: MA0PR01MB9401 On 8/28/2025 7:18 PM, ALOK TIWARI wrote: > > > On 8/28/2025 7:47 AM, Chen Wang wrote: >> From: Chen Wang >> [......] >> + >> +#include >> +#include >> +#include >> +#include >> +#include >> + >> +#include "pcie-cadence.h" >> + >> +/* >> + * SG2042 only support 4-byte aligned access, so for the rootbus >> (i.e. to read > > support -> supports Nice catch! > >> + * the Root Port itself, read32 is required. For non-rootbus (i.e. >> to read >> + * the PCIe peripheral registers, supports 1/2/4 byte aligned >> access, so >> + * directly using read should be fine. >> + * >> + * The same is true for write. > [clip] >> +static int sg2042_pcie_probe(struct platform_device *pdev) >> +{ >> +    struct device *dev = &pdev->dev; >> +    struct pci_host_bridge *bridge; >> +    struct cdns_pcie *pcie; >> +    struct cdns_pcie_rc *rc; >> +    int ret; >> + >> +    pcie = devm_kzalloc(dev, sizeof(*pcie), GFP_KERNEL); >> +    if (!pcie) >> +        return -ENOMEM; >> + >> +    bridge = devm_pci_alloc_host_bridge(dev, sizeof(*rc)); >> +    if (!bridge) { >> +        dev_err(dev, "Failed to alloc host bridge!\n"); >> +        return -ENOMEM; >> +    } >> + >> +    bridge->ops = &sg2042_pcie_host_ops; >> + >> +    rc = pci_host_bridge_priv(bridge); >> +    pcie = &rc->pcie; > First, pcie is allocated and then reassigned to &rc->pcie, > which makes the initial allocation effectively leaked and unnecessary. My fault. Thanks, Chen [......] > > Thanks, > Alok