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From: Chen Wang <unicorn_wang@outlook.com>
To: Manivannan Sadhasivam <mani@kernel.org>, Chen Wang <unicornxw@gmail.com>
Cc: kwilczynski@kernel.org, u.kleine-koenig@baylibre.com,
	aou@eecs.berkeley.edu, alex@ghiti.fr, arnd@arndb.de,
	bwawrzyn@cisco.com, bhelgaas@google.com, conor+dt@kernel.org,
	18255117159@163.com, inochiama@gmail.com, kishon@kernel.org,
	krzk+dt@kernel.org, lpieralisi@kernel.org, palmer@dabbelt.com,
	paul.walmsley@sifive.com, robh@kernel.org, s-vadapalli@ti.com,
	tglx@linutronix.de, thomas.richard@bootlin.com,
	sycamoremoon376@gmail.com, devicetree@vger.kernel.org,
	linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org,
	linux-riscv@lists.infradead.org, sophgo@lists.linux.dev,
	rabenda.cn@gmail.com, chao.wei@sophgo.com,
	xiaoguang.xing@sophgo.com, fengchun.li@sophgo.com
Subject: Re: [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host
Date: Mon, 1 Sep 2025 14:17:20 +0800	[thread overview]
Message-ID: <MAUPR01MB11072CCB9E907768E89660F2DFE07A@MAUPR01MB11072.INDPRD01.PROD.OUTLOOK.COM> (raw)
In-Reply-To: <qyr73crraruct5dgxfko75gv2mrrxxolkzqnu3bngfelcobgfa@wc4rrzfs27gp>


On 8/31/2025 12:47 PM, Manivannan Sadhasivam wrote:
> On Thu, Aug 28, 2025 at 10:16:54AM GMT, Chen Wang wrote:
>> From: Chen Wang <unicorn_wang@outlook.com>
>>
>> Add binding for Sophgo SG2042 PCIe host controller.
>>
>> Signed-off-by: Chen Wang <unicorn_wang@outlook.com>
>> ---
>>   .../bindings/pci/sophgo,sg2042-pcie-host.yaml | 66 +++++++++++++++++++
>>   1 file changed, 66 insertions(+)
>>   create mode 100644 Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>>
>> diff --git a/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>> new file mode 100644
>> index 000000000000..2cca3d113d11
>> --- /dev/null
>> +++ b/Documentation/devicetree/bindings/pci/sophgo,sg2042-pcie-host.yaml
>> @@ -0,0 +1,66 @@
>> +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause)
>> +%YAML 1.2
>> +---
>> +$id: http://devicetree.org/schemas/pci/sophgo,sg2042-pcie-host.yaml#
>> +$schema: http://devicetree.org/meta-schemas/core.yaml#
>> +
>> +title: Sophgo SG2042 PCIe Host (Cadence PCIe Wrapper)
>> +
>> +description:
>> +  Sophgo SG2042 PCIe host controller is based on the Cadence PCIe core.
>> +
>> +maintainers:
>> +  - Chen Wang <unicorn_wang@outlook.com>
>> +
>> +properties:
>> +  compatible:
>> +    const: sophgo,sg2042-pcie-host
>> +
>> +  reg:
>> +    maxItems: 2
>> +
>> +  reg-names:
>> +    items:
>> +      - const: reg
>> +      - const: cfg
>> +
>> +  vendor-id:
>> +    const: 0x1f1c
>> +
>> +  device-id:
>> +    const: 0x2042
>> +
>> +  msi-parent: true
>> +
>> +allOf:
>> +  - $ref: cdns-pcie-host.yaml#
>> +
>> +required:
>> +  - compatible
>> +  - reg
>> +  - reg-names
>> +  - vendor-id
>> +  - device-id
> Why are these IDs 'required'? The default IDs are invalid?

I find the default IDs I read from the SoC is still that for Cadence, it 
would confused when I run lspci, so I replace the IDs for Sophgo.

Anyway, it's ok for me to remove IDs as "required" in bindings but still 
set it in DTS.

Thanks,

Chen

>
> - Mani
>

  reply	other threads:[~2025-09-01  6:17 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-08-28  2:15 [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2025-08-28  2:16 ` [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2025-08-29 17:13   ` Rob Herring (Arm)
2025-08-31  4:47   ` Manivannan Sadhasivam
2025-09-01  6:17     ` Chen Wang [this message]
2025-08-28  2:17 ` [PATCH 2/5] PCI: cadence: Fix NULL pointer error for ops Chen Wang
2025-08-28 21:43   ` Bjorn Helgaas
2025-08-29  0:16     ` Chen Wang
2025-08-28  2:17 ` [PATCH 3/5] PCI: sg2042: Add Sophgo SG2042 PCIe driver Chen Wang
2025-08-28 11:18   ` ALOK TIWARI
2025-08-29  0:12     ` Chen Wang
2025-08-29 17:09   ` Rob Herring
2025-08-30  1:42     ` Chen Wang
2025-08-31  4:45   ` Manivannan Sadhasivam
2025-09-01  6:00     ` Chen Wang
2025-08-28  2:18 ` [PATCH 4/5] riscv: sophgo: dts: add pcie controllers for SG2042 Chen Wang
2025-08-28  2:18 ` [PATCH 5/5] riscv: sophgo: dts: enable pcie for PioneerBox Chen Wang
  -- strict thread matches above, loose matches on Subject: below --
2024-11-11  5:59 [PATCH 0/5] Add PCIe support to Sophgo SG2042 SoC Chen Wang
2024-11-11  5:59 ` [PATCH 1/5] dt-bindings: pci: Add Sophgo SG2042 PCIe host Chen Wang
2024-11-12 15:59   ` Rob Herring
2024-11-14  2:51     ` Chen Wang

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