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Wed, 29 Jan 2020 11:16:47 +0000 From: Bharat Kumar Gogada To: Bjorn Helgaas CC: "linux-pci@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Ravikiran Gummaluri Subject: RE: [PATCH v4 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Thread-Topic: [PATCH v4 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port driver Thread-Index: AQHV1djPdcy89P+RjEyUcJUFKy6DOKgAG/4AgAFMXfA= Date: Wed, 29 Jan 2020 11:16:47 +0000 Message-ID: References: <1580215483-8835-3-git-send-email-bharat.kumar.gogada@xilinx.com> <20200128140424.GA150109@google.com> In-Reply-To: <20200128140424.GA150109@google.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-Auto-Response-Suppress: DR, RN, NRN, OOF, AutoReply X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=bharatku@xilinx.com; x-originating-ip: [149.199.50.133] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: e3d9e331-878a-44bc-7e59-08d7a4acbafa x-ms-traffictypediagnostic: MN2PR02MB7085:|MN2PR02MB7085: x-ms-exchange-transport-forked: True x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:1751; 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charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: xilinx.com X-MS-Exchange-CrossTenant-Network-Message-Id: e3d9e331-878a-44bc-7e59-08d7a4acbafa X-MS-Exchange-CrossTenant-originalarrivaltime: 29 Jan 2020 11:16:47.2444 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 657af505-d5df-48d0-8300-c31994686c5c X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: NGC8bh8clMSTzNqWCYQJTd2NIWDDG0U9/BP9/5MWUXSAQPSl1/U/+X3wbD5lnBqt0CmNAPKA6cg1SvYoOovpig== X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN2PR02MB7085 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org > Subject: Re: [PATCH v4 2/2] PCI: xilinx-cpm: Add Versal CPM Root Port dri= ver >=20 > On Tue, Jan 28, 2020 at 06:14:43PM +0530, Bharat Kumar Gogada wrote: > > - Add support for Versal CPM as Root Port. > > - The Versal ACAP devices include CCIX-PCIe Module (CPM). The integrate= d > > block for CPM along with the integrated bridge can function > > as PCIe Root Port. > > - CPM Versal uses GICv3 ITS feature for achieving assigning MSI/MSI-X > > vectors and handling MSI/MSI-X interrupts. > > - Bridge error and legacy interrupts in Versal CPM are handled using > > Versal CPM specific MISC interrupt line. > > > > Changes v4: > > - change commit subject. > > - Remove unnecessary comments and type cast. > > - Added comments for CPM block register access using readl/writel. > > > > Signed-off-by: Bharat Kumar Gogada > > ... >=20 > > +static bool xilinx_cpm_pcie_valid_device(struct pci_bus *bus, > > + unsigned int devfn) > > +{ > > + struct xilinx_cpm_pcie_port *port =3D bus->sysdata; > > + > > + /* Only one device down on each root port */ > > + if (bus->number =3D=3D port->root_busno && devfn > 0) > > + return false; >=20 > This whole *_valid_device() thing is a mess. We shouldn't need it at all= . But if > we *do* need it, I don't think you should check the entire devfn because = that > means you can't attach a multifunction device. >=20 > Several other drivers with similar *_valid_device() implementations check= only > PCI_SLOT(): >=20 > dw_pcie_valid_device() > advk_pcie_valid_device() > pci_dw_valid_device() > altera_pcie_valid_device() > mobiveil_pcie_valid_device() > rockchip_pcie_valid_device() >=20 > Even checking just PCI_SLOT() is problematic because I think an ARI devic= e with > more than 8 functions will not work correctly. >=20 > What exactly happens if you omit this function, i.e., if we just go ahead= and > attempt config accesses when the device is not present? We > *should* get something like an Unsupported Request completion, and that > *should* be a recoverable error. Most hardware turns this error into rea= d data > of 0xffffffff. The OS should be able to figure out that there's no devic= e there > and continue with no ill effects. >=20 Thanks Bjorn. I did test and I do not see any issue without this.=20 Will resend patch with this change. > > + return true; > > +} > > + > > +/** > > + * xilinx_cpm_pcie_map_bus - Get configuration base > > + * @bus: PCI Bus structure > > + * @devfn: Device/function > > + * @where: Offset from base > > + * > > + * Return: Base address of the configuration space needed to be > > + * accessed. > > + */ > > +static void __iomem *xilinx_cpm_pcie_map_bus(struct pci_bus *bus, > > + unsigned int devfn, int where) { > > + struct xilinx_cpm_pcie_port *port =3D bus->sysdata; > > + int relbus; > > + > > + if (!xilinx_cpm_pcie_valid_device(bus, devfn)) > > + return NULL; > > + > > + relbus =3D (bus->number << ECAM_BUS_NUM_SHIFT) | > > + (devfn << ECAM_DEV_NUM_SHIFT); > > + > > + return port->reg_base + relbus + where; } > > + > > +/* PCIe operations */ > > +static struct pci_ops xilinx_cpm_pcie_ops =3D { > > + .map_bus =3D xilinx_cpm_pcie_map_bus, > > + .read =3D pci_generic_config_read, > > + .write =3D pci_generic_config_write, > > +}; Regards, bharat