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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from SJ2PR12MB9161.namprd12.prod.outlook.com (2603:10b6:a03:566::20) by MW4PR12MB7014.namprd12.prod.outlook.com (2603:10b6:303:218::8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.546.14; Tue, 20 Oct 2026 07:50:38 +0000 Received: from SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017]) by SJ2PR12MB9161.namprd12.prod.outlook.com ([fe80::d9d1:8c49:a703:b017%5]) with mapi id 15.21.0546.012; Tue, 20 Oct 2026 07:50:38 +0000 From: Mikko Perttunen To: Thierry Reding , Jonathan Hunter , Uwe =?UTF-8?B?S2xlaW5lLUvDtm5pZw==?= Cc: linux-pwm@vger.kernel.org, linux-tegra@vger.kernel.org, linux-kernel@vger.kernel.org, Sashiko Subject: Re: [PATCH] pwm: tegra: Fix value discarding for duty and period Date: Tue, 20 Oct 2026 16:50:34 +0900 Message-ID: In-Reply-To: <20261015085336.4181137-2-u.kleine-koenig@baylibre.com> References: <20261015085336.4181137-2-u.kleine-koenig@baylibre.com> Content-Transfer-Encoding: quoted-printable Content-Type: text/plain; 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Make these parameters u64 instead of int > to not lose the upper bits for bigger values. If such a discard happens > the values that are written to hardware become wrong, or (if the > discarded period value becomes 0) a division by zero happens. >=20 > Adapt the math functions accordingly to not let the now potentially > bigger values result in overflows. >=20 > Reported-by: Sashiko > Link: https://sashiko.dev/#/bug/linux-5c5b97d6-4da6-4d06-9dc7-957419dcd83= 2 > Fixes: fd3ddd4355c0 ("pwm: tegra: Implement .apply() callback") > Signed-off-by: Uwe Kleine-K=C3=B6nig > --- > Hello, >=20 > actually the Fixes: line isn't quite accurate. The problem that the > arguments are cropped to int from u64 exists since v4.7-rc1 (commit > 5ec803edcb70 ("pwm: Add core infrastructure to allow atomic updates")) > in the pwm core, but the blamed commit above is the commit where this > problem was moved to the pwm-tegra driver and thus it's fixable there. > The problem in the core doesn't exist any more since commit 0829c35dc534 > ("pwm: Drop support for legacy drivers") in v6.0-rc1. >=20 > Note this patch changes the rounding of the duty cycle (from somewhat > round closest to somewhat round down). It would not be hard to keep the > behaviour by introducing a variant of mul_u64_u64_div_u64() that rounds > closest, but the rounding is spoiled anyhow by later rounding of the > period. To actually fix that it would be best to convert the driver to > the waveform callbacks. >=20 > Example calculation: Let's assume an input clock (pc->clk_rate) of > 100000 Hz and a request with period_ns =3D 230399744 and > duty_ns =3D 128249857. To translate that into register settings the > DUTY_SHIFT values will be round down with both approaches and result in > an actual duty_cycle of 127658000 ns (=CE=94 =3D -591857 ns) while 128557= 000 ns > (=CE=94 =3D 307143 ns) would also be possible. >=20 > Best regards > Uwe >=20 > drivers/pwm/pwm-tegra.c | 11 +++++------ > 1 file changed, 5 insertions(+), 6 deletions(-) >=20 > diff --git a/drivers/pwm/pwm-tegra.c b/drivers/pwm/pwm-tegra.c > index 5cdbe120ba2d..8b5ed7998fdd 100644 > --- a/drivers/pwm/pwm-tegra.c > +++ b/drivers/pwm/pwm-tegra.c > @@ -138,22 +138,21 @@ static inline void tegra_pwm_writel(struct pwm_devi= ce *pwm, unsigned int offset, > } > =20 > static int tegra_pwm_config(struct pwm_chip *chip, struct pwm_device *pw= m, > - int duty_ns, int period_ns) > + u64 duty_ns, u64 period_ns) > { > struct tegra_pwm_chip *pc =3D to_tegra_pwm_chip(chip); > - unsigned long long c =3D duty_ns; > unsigned long rate, required_clk_rate; > u32 val =3D 0; > int err; > + u64 c; > =20 > /* > * Convert from duty_ns / period_ns to a fixed number of duty ticks > - * per TEGRA_PWM_DEPTH cycles and make sure to round to the > - * nearest integer during division. > + * per TEGRA_PWM_DEPTH cycles. > */ > - c *=3D TEGRA_PWM_DEPTH; > - c =3D DIV_ROUND_CLOSEST_ULL(c, period_ns); > + c =3D mul_u64_u64_div_u64(duty_ns, TEGRA_PWM_DEPTH, period_ns); > =20 > + /* The cast here is fine as c <=3D TEGRA_PWM_DEPTH */ > val =3D (u32)c << TEGRA_PWM_DUTY_SHIFT; The change looks good to me, but the required clock rate calculation=20 further below should also be updated accordingly. Thanks Mikko > =20 > /* >=20 > base-commit: 00e917df050d79ac26ec700717680ad6421d2808 > --=20 > 2.56.0.rc1 >=20 >=20