From: "James Washer" <washer@us.ibm.com>
To: Alan Cox <alan@lxorguk.ukuu.org.uk>, <linux-kernel@vger.kernel.org>
Subject: Re: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell box
Date: Wed, 20 Mar 2002 16:30:18 -0800 [thread overview]
Message-ID: <OF144873DD.BC645CDA-ON87256B83.0000EE37@boulder.ibm.com> (raw)
The iTLB would be flushed when he did the reload of cr3 ( per your
suggestion ) UNLESS the G bit was set.
I suppose theres some small chance, that at the time this instruction was
first cached and its corresponding iTLB entry was loaded, the G bit may
have been set.. Seems unlikely. but I'll hack up something to
unconditionally flush the iTLB.
- jim
Alan Cox <alan@lxorguk.ukuu.org.uk>@vger.kernel.org on 03/20/2002 04:04:51
PM
Sent by: linux-kernel-owner@vger.kernel.org
To: kurt@garloff.de (Kurt Garloff)
cc: tepperly@llnl.gov (Tom Epperly), linux-kernel@vger.kernel.org (Linux
kernel list)
Subject: Re: Bad Illegal instruction traps on dual-Xeon (p4) Linux Dell
box
> disassembly?
> AFAICS, its a push %ebp instruction, which should not be illegal. So
either
> your stack is overflowing or my suspicion with the defect CPU is
applicable.
Or somehow the I/D TLB's got messed up and the ITLB for that entry is now
wrong.
-
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next reply other threads:[~2002-03-21 0:30 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-03-21 0:30 James Washer [this message]
2002-03-21 7:19 ` Zwane Mwaikambo
-- strict thread matches above, loose matches on Subject: below --
2002-03-21 14:52 James Washer
2002-03-20 23:46 James Washer
2002-03-20 21:35 Tom Epperly
2002-03-20 23:26 ` Kurt Garloff
2002-03-21 0:04 ` Alan Cox
2002-03-20 23:31 ` Alan Cox
2002-03-20 23:31 ` Tom Epperly
2002-03-21 0:03 ` Dave Jones
2002-03-21 0:04 ` Alan Cox
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