From: Ryan Chen <ryan_chen@aspeedtech.com>
To: Thomas Gleixner <tglx@linutronix.de>,
Eddie James <eajames@linux.ibm.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>, Joel Stanley <joel@jms.id.au>,
Andrew Jeffery <andrew@codeconstruct.com.au>,
"linux-aspeed@lists.ozlabs.org" <linux-aspeed@lists.ozlabs.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>,
"devicetree@vger.kernel.org" <devicetree@vger.kernel.org>,
"linux-arm-kernel@lists.infradead.org"
<linux-arm-kernel@lists.infradead.org>
Subject: RE: [PATCH 2/2] irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers
Date: Wed, 6 Aug 2025 06:43:27 +0000 [thread overview]
Message-ID: <OS8PR06MB7541C713096CA46636AECEE4F22DA@OS8PR06MB7541.apcprd06.prod.outlook.com> (raw)
In-Reply-To: <874iumgqar.ffs@tglx>
> Subject: Re: [PATCH 2/2] irqchip/aspeed-scu-ic: Add support for AST2700 SCU
> interrupt controllers
>
> On Mon, Aug 04 2025 at 13:34, Ryan Chen wrote:
> > +#define ASPEED_AST2700_SCU_IC0_EN_REG 0x1d0
> > +#define ASPEED_AST2700_SCU_IC0_STS_REG 0x1d4
> > +#define ASPEED_AST2700_SCU_IC0_SHIFT 0
> > +#define ASPEED_AST2700_SCU_IC0_ENABLE \
> > + GENMASK(3, ASPEED_AST2700_SCU_IC0_SHIFT)
>
> Let it stick out, you have 100 characters
Yes, will update to
#define ASPEED_AST2700_SCU_IC0_ENABLE GENMASK(3, ASPEED_AST2700_SCU_IC0_SHIFT)
And another question, in original code define for AST2600, can I also modify it in this patch?
or I should be another patch?
#define ASPEED_AST2600_SCU_IC1_ENABLE \
GENMASK(5, ASPEED_AST2600_SCU_IC1_SHIFT)
>
> > struct aspeed_scu_ic {
> > unsigned long irq_enable;
> > unsigned long irq_shift;
> > unsigned int num_irqs;
> > unsigned int reg;
> > + unsigned int en_reg;
> > + unsigned int sts_reg;
> > + bool split_ier_isr;
>
> Please reformat this struct declaration according to:
>
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#struct-de
> clarations-and-initializers
Will update struct aspeed_scu_ic to following.
struct aspeed_scu_ic {
unsigned long irq_enable;
unsigned long irq_shift;
unsigned int num_irqs;
unsigned int reg;
unsigned int en_reg;
unsigned int sts_reg;
bool split_ier_isr;
struct regmap *scu;
struct irq_domain *irq_domain;
};
>
> > struct regmap *scu;
> > struct irq_domain *irq_domain;
> > };
> > @@ -52,33 +83,51 @@ static void aspeed_scu_ic_irq_handler(struct
> irq_desc *desc)
> > unsigned long status;
> > struct aspeed_scu_ic *scu_ic = irq_desc_get_handler_data(desc);
> > struct irq_chip *chip = irq_desc_get_chip(desc);
> > - unsigned int mask = scu_ic->irq_enable <<
> ASPEED_SCU_IC_STATUS_SHIFT;
> > + unsigned int mask;
>
> https://www.kernel.org/doc/html/latest/process/maintainer-tip.html#variable-
> declarations
Will update by following.
struct aspeed_scu_ic *scu_ic;
struct irq_chip *chip;
unsigned long bit, enabled, max, status;
unsigned int sts, mask;
scu_ic = irq_desc_get_handler_data(desc);
chip = irq_desc_get_chip(desc);
>
> > chained_irq_enter(chip, desc);
> >
> > - /*
> > - * The SCU IC has just one register to control its operation and read
> > - * status. The interrupt enable bits occupy the lower 16 bits of the
> > - * register, while the interrupt status bits occupy the upper 16 bits.
> > - * The status bit for a given interrupt is always 16 bits shifted from
> > - * the enable bit for the same interrupt.
> > - * Therefore, perform the IRQ operations in the enable bit space by
> > - * shifting the status down to get the mapping and then back up to
> > - * clear the bit.
> > - */
> > - regmap_read(scu_ic->scu, scu_ic->reg, &sts);
> > - enabled = sts & scu_ic->irq_enable;
> > - status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
> > -
> > - bit = scu_ic->irq_shift;
> > - max = scu_ic->num_irqs + bit;
> > -
> > - for_each_set_bit_from(bit, &status, max) {
> > - generic_handle_domain_irq(scu_ic->irq_domain,
> > - bit - scu_ic->irq_shift);
> > -
> > - regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
> > - BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
> > + if (scu_ic->split_ier_isr) {
> > + mask = scu_ic->irq_enable;
> > + regmap_read(scu_ic->scu, scu_ic->en_reg, &sts);
> > + enabled = sts & scu_ic->irq_enable;
> > + regmap_read(scu_ic->scu, scu_ic->sts_reg, &sts);
> > + status = sts & enabled;
> > +
> > + bit = scu_ic->irq_shift;
> > + max = scu_ic->num_irqs + bit;
> > +
> > + for_each_set_bit_from(bit, &status, max) {
> > + generic_handle_domain_irq(scu_ic->irq_domain, bit -
> > +scu_ic->irq_shift);
> > +
> > + regmap_write_bits(scu_ic->scu, scu_ic->sts_reg, mask, BIT(bit));
> > + }
> > + } else {
> > + mask = scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT;
> > + /*
> > + * The SCU IC has just one register to control its operation and read
> > + * status. The interrupt enable bits occupy the lower 16 bits of the
> > + * register, while the interrupt status bits occupy the upper 16 bits.
> > + * The status bit for a given interrupt is always 16 bits shifted from
> > + * the enable bit for the same interrupt.
> > + * Therefore, perform the IRQ operations in the enable bit space by
> > + * shifting the status down to get the mapping and then back up to
> > + * clear the bit.
> > + */
> > + regmap_read(scu_ic->scu, scu_ic->reg, &sts);
> > + enabled = sts & scu_ic->irq_enable;
> > + status = (sts >> ASPEED_SCU_IC_STATUS_SHIFT) & enabled;
> > +
> > + bit = scu_ic->irq_shift;
> > + max = scu_ic->num_irqs + bit;
> > +
> > + for_each_set_bit_from(bit, &status, max) {
> > + generic_handle_domain_irq(scu_ic->irq_domain,
> > + bit - scu_ic->irq_shift);
> > +
> > + regmap_write_bits(scu_ic->scu, scu_ic->reg, mask,
> > + BIT(bit + ASPEED_SCU_IC_STATUS_SHIFT));
> > + }
>
> This is horrible, really. Either rework the code so that both chips can share it
> with minimal conditionals or provide seperate handlers. It's not rocket science.
Yes, I will update by separate handlers.
older
static struct irq_chip aspeed_scu_ic_chip = {
.name = "aspeed-scu-ic",
.irq_mask = aspeed_scu_ic_irq_mask,
.irq_unmask = aspeed_scu_ic_irq_unmask,
.irq_set_affinity = aspeed_scu_ic_irq_set_affinity,
};
Add new
static struct irq_chip ast2700_scu_ic_chip = {
.name = "aspeed-scu-ic",
.irq_mask = ast2700_scu_ic_irq_mask,
.irq_unmask = ast2700_scu_ic_irq_unmask,
.irq_set_affinity = ast2700_scu_ic_irq_set_affinity,
};
if (scu_ic->split_ier_isr)
irq_set_chained_handler_and_data(irq, ast2700_scu_ic_irq_handler, scu_ic);
else
irq_set_chained_handler_and_data(irq, aspeed_scu_ic_irq_handler,, scu_ic);
>
> > chained_irq_exit(chip, desc);
> > @@ -87,30 +136,42 @@ static void aspeed_scu_ic_irq_handler(struct
> > irq_desc *desc)
>
> > static void aspeed_scu_ic_irq_mask(struct irq_data *data) static
> > void aspeed_scu_ic_irq_unmask(struct irq_data *data)
>
> > {
> > struct aspeed_scu_ic *scu_ic = irq_data_get_irq_chip_data(data);
> > unsigned int bit = BIT(data->hwirq + scu_ic->irq_shift);
> > - unsigned int mask = bit |
> > - (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
> > -
> > - /*
> > - * Status bits are cleared by writing 1. In order to prevent the unmask
> > - * operation from clearing the status bits, they should be under the
> > - * mask and written with 0.
> > - */
> > - regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);
> > + unsigned int mask;
> > +
> > + if (scu_ic->split_ier_isr) {
> > + mask = bit;
> > + regmap_update_bits(scu_ic->scu, scu_ic->en_reg, mask, bit);
> > + } else {
> > + mask = bit | (scu_ic->irq_enable << ASPEED_SCU_IC_STATUS_SHIFT);
> > +
> > + /*
> > + * Status bits are cleared by writing 1. In order to prevent the
> unmask
> > + * operation from clearing the status bits, they should be under the
> > + * mask and written with 0.
> > + */
> > + regmap_update_bits(scu_ic->scu, scu_ic->reg, mask, bit);
> > + }
>
> This also wants to be consolidated or seperated.
Yes, will do separated.
>
> > }
> >
> > +static int __init aspeed_ast2700_scu_ic0_of_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
> > +
> > + if (!scu_ic)
> > + return -ENOMEM;
> > +
> > + scu_ic->irq_enable = ASPEED_AST2700_SCU_IC0_ENABLE;
> > + scu_ic->irq_shift = ASPEED_AST2700_SCU_IC0_SHIFT;
> > + scu_ic->num_irqs = ASPEED_AST2700_SCU_IC0_NUM_IRQS;
> > + scu_ic->split_ier_isr = true;
> > + scu_ic->en_reg = ASPEED_AST2700_SCU_IC0_EN_REG;
> > + scu_ic->sts_reg = ASPEED_AST2700_SCU_IC0_STS_REG;
> > +
> > + return aspeed_scu_ic_of_init_common(scu_ic, node); }
> > +
> > +static int __init aspeed_ast2700_scu_ic1_of_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
> > +
> > + if (!scu_ic)
> > + return -ENOMEM;
> > +
> > + scu_ic->irq_enable = ASPEED_AST2700_SCU_IC1_ENABLE;
> > + scu_ic->irq_shift = ASPEED_AST2700_SCU_IC1_SHIFT;
> > + scu_ic->num_irqs = ASPEED_AST2700_SCU_IC1_NUM_IRQS;
> > + scu_ic->split_ier_isr = true;
> > + scu_ic->en_reg = ASPEED_AST2700_SCU_IC1_EN_REG;
> > + scu_ic->sts_reg = ASPEED_AST2700_SCU_IC1_STS_REG;
> > +
> > + return aspeed_scu_ic_of_init_common(scu_ic, node); }
> > +
> > +static int __init aspeed_ast2700_scu_ic2_of_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
> > +
> > + if (!scu_ic)
> > + return -ENOMEM;
> > +
> > + scu_ic->irq_enable = ASPEED_AST2700_SCU_IC2_ENABLE;
> > + scu_ic->irq_shift = ASPEED_AST2700_SCU_IC2_SHIFT;
> > + scu_ic->num_irqs = ASPEED_AST2700_SCU_IC2_NUM_IRQS;
> > + scu_ic->split_ier_isr = true;
> > + scu_ic->en_reg = ASPEED_AST2700_SCU_IC2_EN_REG;
> > + scu_ic->sts_reg = ASPEED_AST2700_SCU_IC2_STS_REG;
> > +
> > + return aspeed_scu_ic_of_init_common(scu_ic, node); }
> > +
> > +static int __init aspeed_ast2700_scu_ic3_of_init(struct device_node *node,
> > + struct device_node *parent)
> > +{
> > + struct aspeed_scu_ic *scu_ic = kzalloc(sizeof(*scu_ic), GFP_KERNEL);
> > +
> > + if (!scu_ic)
> > + return -ENOMEM;
> > +
> > + scu_ic->irq_enable = ASPEED_AST2700_SCU_IC3_ENABLE;
> > + scu_ic->irq_shift = ASPEED_AST2700_SCU_IC3_SHIFT;
> > + scu_ic->num_irqs = ASPEED_AST2700_SCU_IC3_NUM_IRQS;
> > + scu_ic->split_ier_isr = true;
> > + scu_ic->en_reg = ASPEED_AST2700_SCU_IC3_EN_REG;
> > + scu_ic->sts_reg = ASPEED_AST2700_SCU_IC3_STS_REG;
> > +
> > + return aspeed_scu_ic_of_init_common(scu_ic, node); }
>
> You seriously have no better idea than this copy & pasta orgy?
>
> static struct scu_variant variants = {
> SCU("aspeed,ast2400-scu-ic", ......, whatever...),
> ...
> SCU("aspeed,ast2700-scu-ic0", 0x1D0, 0x1D4, 0, GENMASK(3, 0),
> 4, whatever...),
> ...
> SCU("aspeed,ast2700-scu-ic3", 0x10C, 0x108, 0, GENMASK(1, 0),
> 2, ......),
> } __initdata;
>
> static struct scu_variant *find_variant(struct device_node *node) {
> for (int i = 0; i < ARRAY_SIZE(variant); i++) {
> if (!strcmp(variant[i].name, node->name))
> return &variant[i];
> }
> return NULL;
> }
>
> static int __init ast_scu_of_init(struct device_node *node, struct device_node
> *parent) {
> struct variant *v = find_variant(node);
>
> if (!v)
> ...
>
> scu_ic = kzalloc(...);
> *scu_ic = v->scu;
> ...
>
> You get the idea.
>
Thanks, I will do rework first, then add AST2700.
> This rework needs to come first and then you can add your new 2700 muck on
> top.
>
> Thanks,
>
> tglx
next prev parent reply other threads:[~2025-08-06 6:43 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-04 5:34 [PATCH 0/2] irqchip: Add support for Aspeed AST2700 SCU interrupt controller Ryan Chen
2025-08-04 5:34 ` [PATCH 1/2] dt-bindings: interrupt-controller: aspeed: add AST2700 SCU IC compatibles Ryan Chen
2025-08-04 7:32 ` Krzysztof Kozlowski
2025-08-05 1:39 ` Ryan Chen
2025-08-04 5:34 ` [PATCH 2/2] irqchip/aspeed-scu-ic: Add support for AST2700 SCU interrupt controllers Ryan Chen
2025-08-05 7:50 ` Thomas Gleixner
2025-08-06 6:43 ` Ryan Chen [this message]
2025-08-05 15:39 ` Rob Herring
2025-08-06 7:14 ` Ryan Chen
2025-08-06 13:41 ` Eddie James
2025-08-06 14:44 ` Thomas Gleixner
2025-08-07 0:23 ` Ryan Chen
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