From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1753966AbeDJNeC (ORCPT ); Tue, 10 Apr 2018 09:34:02 -0400 Received: from relmlor2.renesas.com ([210.160.252.172]:64723 "EHLO relmlie1.idc.renesas.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1752907AbeDJNeA (ORCPT ); Tue, 10 Apr 2018 09:34:00 -0400 X-IronPort-AV: E=Sophos;i="5.48,432,1517842800"; d="scan'208";a="277780393" From: Biju Das To: Geert Uytterhoeven , Michael Turquette , Stephen Boyd CC: "linux-renesas-soc@vger.kernel.org" , "linux-clk@vger.kernel.org" , "linux-kernel@vger.kernel.org" Subject: RE: [PATCH] clk: renesas: rcar-gen2: Centralize quirks handling Thread-Topic: [PATCH] clk: renesas: rcar-gen2: Centralize quirks handling Thread-Index: AQHT0MyTD4lvxsMAREeMz70E3UkXuKP5/nWg Date: Tue, 10 Apr 2018 13:33:55 +0000 Message-ID: References: <1523365498-16789-1-git-send-email-geert+renesas@glider.be> In-Reply-To: <1523365498-16789-1-git-send-email-geert+renesas@glider.be> Accept-Language: en-GB, en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: spf=none (sender IP is ) smtp.mailfrom=biju.das@bp.renesas.com; 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x-microsoft-antispam-message-info: FOBOG6KrgHX5kVo69aV5wVRff2OT8xzPHQH1RZWjz/dD6K8jECdlHa1U3g51MYBQ2mjPRdOiYKfKhDJItJ44vzMjUDqkDf6ANolBNI+586LK89oqtBd5A/lWJ0I8tqxD5zzQX3dT4DGppff/QgeZNJeri4IyCigQcJAsJPK900GGL0Ddz5qpOxgozmYwpIwV5IANpxRaU/9bEHcUYC+5nr42c/M/3rjj6rH8WQ0gGiLYY2/Kcp5xHfR2+fvyFs4JnVGhTX0MxSiO3PsVydg93wNbau0zWxzX9abMpjU6ev4IofwLTj0Y6Oiy/0/kCtlS/n++iXUIDy2DxbOdcY9p3MZFWBBmFRj1Qek0rAGLjJxToV/Q6lDPlEeHe9hdGZ8IHHDWYdX0MewMoFNtkx5bn8AQJzKcl8b+Cj8GFBerBnY= spamdiagnosticoutput: 1:99 spamdiagnosticmetadata: NSPM Content-Type: text/plain; charset="us-ascii" MIME-Version: 1.0 X-OriginatorOrg: bp.renesas.com X-MS-Exchange-CrossTenant-Network-Message-Id: 44758e85-a70b-4620-ba4c-08d59ee7b562 X-MS-Exchange-CrossTenant-originalarrivaltime: 10 Apr 2018 13:33:55.9167 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSBPR01MB1829 Sender: linux-kernel-owner@vger.kernel.org List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Content-Transfer-Encoding: 8bit X-MIME-Autoconverted: from quoted-printable to 8bit by mail.home.local id w3ADY6lm028547 Hi Geert, Thanks for the patch. > -----Original Message----- > From: Geert Uytterhoeven [mailto:geert+renesas@glider.be] > Sent: 10 April 2018 14:05 > To: Michael Turquette ; Stephen Boyd > ; Biju Das > Cc: linux-renesas-soc@vger.kernel.org; linux-clk@vger.kernel.org; linux- > kernel@vger.kernel.org; Geert Uytterhoeven > Subject: [PATCH] clk: renesas: rcar-gen2: Centralize quirks handling > > Introduce centralized quirks handling like on R-Car Gen3, and convert the > RZ/G1C SD clock table handling over to it. > > This makes it easier to add more quirks later, if/when needed. > > Signed-off-by: Geert Uytterhoeven Reviewed-by: Biju Das > --- > To be queued in clk-renesas-for-v4.18. > > drivers/clk/renesas/rcar-gen2-cpg.c | 20 ++++++++++++++++---- > 1 file changed, 16 insertions(+), 4 deletions(-) > > diff --git a/drivers/clk/renesas/rcar-gen2-cpg.c b/drivers/clk/renesas/rcar- > gen2-cpg.c > index 0c49f59d5074b1c4..daf88bc2cdae177b 100644 > --- a/drivers/clk/renesas/rcar-gen2-cpg.c > +++ b/drivers/clk/renesas/rcar-gen2-cpg.c > @@ -261,9 +261,15 @@ static const struct clk_div_table > cpg_sd01_div_table[] = { static const struct rcar_gen2_cpg_pll_config > *cpg_pll_config __initdata; static unsigned int cpg_pll0_div __initdata; static > u32 cpg_mode __initdata; > +static u32 cpg_quirks __initdata; > > -static const struct soc_device_attribute soc_r8a77470[] = { > -{ .soc_id = "r8a77470" }, > +#define SD_SKIP_FIRSTBIT(0)/* Skip first clock in SD table > */ > + > +static const struct soc_device_attribute cpg_quirks_match[] __initconst = { > +{ > +.soc_id = "r8a77470", > +.data = (void *)SD_SKIP_FIRST, > +}, > { /* sentinel */ } > }; > > @@ -333,7 +339,7 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct > device *dev, > > case CLK_TYPE_GEN2_SD0: > table = cpg_sd01_div_table; > -if (soc_device_match(soc_r8a77470)) > +if (cpg_quirks & SD_SKIP_FIRST) > table++; > > shift = 4; > @@ -341,7 +347,7 @@ struct clk * __init rcar_gen2_cpg_clk_register(struct > device *dev, > > case CLK_TYPE_GEN2_SD1: > table = cpg_sd01_div_table; > -if (soc_device_match(soc_r8a77470)) > +if (cpg_quirks & SD_SKIP_FIRST) > table++; > > shift = 0; > @@ -372,9 +378,15 @@ struct clk * __init > rcar_gen2_cpg_clk_register(struct device *dev, int __init > rcar_gen2_cpg_init(const struct rcar_gen2_cpg_pll_config *config, > unsigned int pll0_div, u32 mode) { > +const struct soc_device_attribute *attr; > + > cpg_pll_config = config; > cpg_pll0_div = pll0_div; > cpg_mode = mode; > +attr = soc_device_match(cpg_quirks_match); > +if (attr) > +cpg_quirks = (uintptr_t)attr->data; > +pr_debug("%s: mode = 0x%x quirks = 0x%x\n", __func__, mode, > +cpg_quirks); > > spin_lock_init(&cpg_lock); > > -- > 2.7.4 Renesas Electronics Europe Ltd, Dukes Meadow, Millboard Road, Bourne End, Buckinghamshire, SL8 5FH, UK. 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