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Thu, 9 Jul 2020 08:26:54 +0000 From: Dien Pham To: Sudeep Holla , "linux-arm-kernel@lists.infradead.org" , "linux-clk@vger.kernel.org" , Stephen Boyd CC: "linux-kernel@vger.kernel.org" , Michael Turquette Subject: RE: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates Thread-Topic: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering clocks with discrete rates Thread-Index: AQHWVcldxf7eBbhrV0WytRuJ2WVzT6j+6QFg Date: Thu, 9 Jul 2020 08:26:54 +0000 Message-ID: References: <20200709081705.46084-1-sudeep.holla@arm.com> <20200709081705.46084-2-sudeep.holla@arm.com> In-Reply-To: <20200709081705.46084-2-sudeep.holla@arm.com> Accept-Language: en-US Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: authentication-results: arm.com; dkim=none (message not signed) header.d=none;arm.com; dmarc=none action=none header.from=renesas.com; x-originating-ip: [210.245.28.11] x-ms-publictraffictype: Email x-ms-office365-filtering-ht: Tenant x-ms-office365-filtering-correlation-id: 3c6301ab-2fa2-484d-9d64-08d823e1d64d x-ms-traffictypediagnostic: OSBPR01MB2711: x-microsoft-antispam-prvs: x-ms-oob-tlc-oobclassifiers: OLM:8273; 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x-ms-exchange-antispam-messagedata: 6Tk8Z6733SByEGTZlyQ4GO6qqCcIbomS7snxdlPz5No18n32HIxz8IcgRe47fnUljSusCUCf2PSQEkWb+m763wI61zNRkaNMKw8LhyODoVrGMpNID0PpaIfdnJ0oJBGVgvo7h8FN8qxJbESRA4PcgqnI/72mjce9JNNycV1dErwwnYwCkKBDW6/oAmrJ2Zrc0B5LSe9ewPT3gL9WCGR1PCCMZgwbKII+mz4j0dqWmu/QWvcB7hkCuFfUkJ4SOI65Jd+WAjhe4bHFXuTYQ/OsDPrrhZLclky4CnHqGdu9VS89JzK+SnuOTXbpQ6pN4X+O6ivL6hSMuWz0RWTYM1YrA5tbzJdXx7d2UuoNrFvgELPmCMoHktFaEg9CCAF2gmcARndHN40wOA7PwLK8n/gL3af6XZsFmLTzQbIQWTCcHFN4l/wwlHhCGLo8f+wg3k0PArtaQHSZsLVPcC3NQQi+BJrA5A3G5liMmmbjh097IBE= x-ms-exchange-transport-forked: True Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 X-OriginatorOrg: renesas.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSBPR01MB4024.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 3c6301ab-2fa2-484d-9d64-08d823e1d64d X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Jul 2020 08:26:54.1310 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 53d82571-da19-47e4-9cb4-625a166a4a2a X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: vwICqxtx0rGNePcvqwK0XehDcygFzDruOekAgmPq6DoT112Q1umVpB+C62Fyie/y99SAB+VXl3llikEkJAHoegrWs5RwPbeeYRVXku4Vbgo= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSBPR01MB2711 Sender: linux-kernel-owner@vger.kernel.org Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Sudeep, Thanks for your patch. >-----Original Message----- >From: Sudeep Holla =20 >Sent: Thursday, July 9, 2020 3:17 PM >To: linux-arm-kernel@lists.infradead.org; linux-clk@vger.kernel.org; Steph= en Boyd >Cc: Sudeep Holla ; linux-kernel@vger.kernel.org; Mic= hael Turquette ; Dien Pham >Subject: [PATCH v2 2/2] clk: scmi: Fix min and max rate when registering c= locks with discrete rates > >Currently we are not initializing the scmi clock with discrete rates corre= ctly. We fetch the min_rate and max_rate value only for clocks with ranges = and ignore the ones with discrete rates. This will lead to wrong initializa= tion of rate range when clock supports discrete rate. > >Fix this by using the first and the last rate in the sorted list of the di= screte clock rates while registering the clock. > >Link: https://lore.kernel.org/r/20200708110725.18017-2-sudeep.holla@arm.co= m >Fixes: 6d6a1d82eaef7 ("clk: add support for clocks provided by SCMI") >Reported-by: Dien Pham >Signed-off-by: Sudeep Holla >--- > drivers/clk/clk-scmi.c | 22 +++++++++++++++++++--- > 1 file changed, 19 insertions(+), 3 deletions(-) > >Hi Stephen, > >If you are fine, I can take this via ARM SoC along with the change in firm= ware driver. However it is also fine if you want to merge this independentl= y as there is no strict dependency. Let me know either way. > >v1[1]->v2: > - Fixed the missing ; which was sent by mistake. I tested the patch, I is ok and can fix my issue. >Regards, >Sudeep > >[1] https://lore.kernel.org/r/20200708110725.18017-2-sudeep.holla@arm.com > >diff --git a/drivers/clk/clk-scmi.c b/drivers/clk/clk-scmi.c index c491f5d= e0f3f..c754dfbb73fd 100644 >--- a/drivers/clk/clk-scmi.c >+++ b/drivers/clk/clk-scmi.c >@@ -103,6 +103,8 @@ static const struct clk_ops scmi_clk_ops =3D { static= int scmi_clk_ops_init(struct device *dev, struct scmi_clk *sclk) { > int ret; >+ unsigned long min_rate, max_rate; >+ > struct clk_init_data init =3D { > .flags =3D CLK_GET_RATE_NOCACHE, > .num_parents =3D 0, >@@ -112,9 +114,23 @@ static int scmi_clk_ops_init(struct device *dev, stru= ct scmi_clk *sclk) >=20 > sclk->hw.init =3D &init; > ret =3D devm_clk_hw_register(dev, &sclk->hw); >- if (!ret) >- clk_hw_set_rate_range(&sclk->hw, sclk->info->range.min_rate, >- sclk->info->range.max_rate); >+ if (ret) >+ return ret; >+ >+ if (sclk->info->rate_discrete) { >+ int num_rates =3D sclk->info->list.num_rates; >+ >+ if (num_rates <=3D 0) >+ return -EINVAL; >+ >+ min_rate =3D sclk->info->list.rates[0]; >+ max_rate =3D sclk->info->list.rates[num_rates - 1]; >+ } else { >+ min_rate =3D sclk->info->range.min_rate; >+ max_rate =3D sclk->info->range.max_rate; >+ } >+ >+ clk_hw_set_rate_range(&sclk->hw, min_rate, max_rate); > return ret; > } >=20 >-- >2.17.1 Best regard, DIEN Pham