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Walleij , Bartosz Golaszewski , Ryan Chen , Andrew Jeffery , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , "linux-clk@vger.kernel.org" Subject: Re: [PATCH v4 2/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl Thread-Topic: [PATCH v4 2/3] dt-bindings: pinctrl: Add aspeed,ast2700-soc0-pinctrl Thread-Index: AQHcrWasfLNWtX5/y0SkB1cDA4lWiLWi5wYAgAkqVmqACwRrwg== Date: Fri, 20 Mar 2026 07:15:00 +0000 Message-ID: References: <20260306-upstream_pinctrl-v4-0-ad4e8ab8b489@aspeedtech.com> <20260306-upstream_pinctrl-v4-2-ad4e8ab8b489@aspeedtech.com> <20260307-weightless-quirky-spoonbill-dacd89@quoll> In-Reply-To: Accept-Language: en-US, zh-TW Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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Internal X-MS-Exchange-CrossTenant-AuthSource: OSQPR06MB7252.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 796fcd23-c4bf-4bcf-f8f5-08de8650666b X-MS-Exchange-CrossTenant-originalarrivaltime: 20 Mar 2026 07:15:00.6909 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: SLu8g6XYOrbY/yEI/6b22UGmDakFO6ZRFtBvovZdieXmCsSqlVgWsVU39MEuFXGTmC7GqDLxn6CypX+SYEsy+mkLG4sfogKTx15APSwIY6Y= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SI3PR06MB8684 ...=0A= =0A= > What remains unclear is how best to model the secondary and tertiary=0A= > service processor control blocks (SSP/TSP) and the PCI control region.=0A= > The SSP and TSP controls consume reserved memory regions used to=0A= > configure the processors' address spaces, while the PCI control region=0A= > contains the VGA scratch registers used to communicate host display=0A= > ownership.=0A= =0A= > The p2a and smp-ram features are supported on earlier generations=0A= > but are not present on AST2700, and should be disabled in the binding=0A= > for the AST2700 as you suggested.=0A= =0A= Hi Krzysztof,=0A= =0A= Following up on my previous email, I've reworked the AST2700 SCU0=0A= binding to better reflect the hardware capabilities and address the=0A= issues discussed.=0A= =0A= In particular:=0A= - Restrict p2a-control and smp-memram for AST2700, as these features=0A= are not present.=0A= - Add SSP/TSP address mapping support using memory-region and=0A= memory-region-names.=0A= - Rework the example so it reflects the AST2700 SCU0 layout and validates= =0A= against the binding schema.=0A= =0A= I wanted to share the current binding update for feedback.=0A= =0A= Below is the current SCU0 binding diff:=0A= =0A= diff --git a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml = b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml=0A= index a87f31fce019..86e560876cf2 100644=0A= --- a/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml=0A= +++ b/Documentation/devicetree/bindings/mfd/aspeed,ast2x00-scu.yaml=0A= @@ -46,6 +46,9 @@ properties:=0A= '#reset-cells':=0A= const: 1=0A= =0A= + memory-region: true=0A= + memory-region-names: true=0A= +=0A= patternProperties:=0A= '^p2a-control@[0-9a-f]+$':=0A= description: >=0A= @@ -87,6 +90,7 @@ patternProperties:=0A= - aspeed,ast2400-pinctrl=0A= - aspeed,ast2500-pinctrl=0A= - aspeed,ast2600-pinctrl=0A= + - aspeed,ast2700-soc0-pinctrl=0A= =0A= required:=0A= - compatible=0A= @@ -156,6 +160,42 @@ required:=0A= - '#clock-cells'=0A= - '#reset-cells'=0A= =0A= +allOf:=0A= + - if:=0A= + properties:=0A= + compatible:=0A= + contains:=0A= + anyOf:=0A= + - const: aspeed,ast2700-scu0=0A= + - const: aspeed,ast2700-scu1=0A= + then:=0A= + patternProperties:=0A= + '^p2a-control@[0-9a-f]+$': false=0A= + '^smp-memram@[0-9a-f]+$': false=0A= +=0A= + - if:=0A= + properties:=0A= + compatible:=0A= + contains:=0A= + const: aspeed,ast2700-scu0=0A= + then:=0A= + properties:=0A= + memory-region:=0A= + items:=0A= + - description: Region mapped through the first SSP address win= dow.=0A= + - description: Region mapped through the second SSP address wi= ndow.=0A= + - description: Region mapped through the TSP address window.= =0A= +=0A= + memory-region-names:=0A= + items:=0A= + - const: ssp-0=0A= + - const: ssp-1=0A= + - const: tsp=0A= + else:=0A= + properties:=0A= + memory-region: false=0A= + memory-region-names: false=0A= +=0A= additionalProperties: false=0A= =0A= examples:=0A= @@ -180,4 +220,81 @@ examples:=0A= reg =3D <0x7c 0x4>, <0x150 0x8>;=0A= };=0A= };=0A= +=0A= + - |=0A= + / {=0A= + #address-cells =3D <2>;=0A= + #size-cells =3D <2>;=0A= +=0A= + reserved-memory {=0A= + #address-cells =3D <2>;=0A= + #size-cells =3D <2>;=0A= + ranges;=0A= +=0A= + ssp_region_0: memory@90000000 {=0A= + reg =3D <0x4 0x00000000 0x0 0x01000000>;=0A= + no-map;=0A= + };=0A= +=0A= + ssp_region_1: memory@91000000 {=0A= + reg =3D <0x4 0x01000000 0x0 0x01000000>;=0A= + no-map;=0A= + };=0A= +=0A= + tsp_region: memory@92000000 {=0A= + reg =3D <0x4 0x02000000 0x0 0x01000000>;=0A= + no-map;=0A= + };=0A= + };=0A= +=0A= + bus {=0A= + #address-cells =3D <2>;=0A= + #size-cells =3D <2>;=0A= +=0A= + syscon@12c02000 {=0A= + compatible =3D "aspeed,ast2700-scu0", "syscon", "simple-mf= d";=0A= + reg =3D <0 0x12c02000 0 0x1000>;=0A= + ranges =3D <0x0 0x0 0x12c02000 0x1000>;=0A= + #address-cells =3D <1>;=0A= + #size-cells =3D <1>;=0A= + #clock-cells =3D <1>;=0A= + #reset-cells =3D <1>;=0A= +=0A= + memory-region =3D <&ssp_region_0>, <&ssp_region_1>,=0A= + <&tsp_region>;=0A= + memory-region-names =3D "ssp-0", "ssp-1", "tsp";=0A= +=0A= + silicon-id@0 {=0A= + compatible =3D "aspeed,ast2700-silicon-id", "aspeed,si= licon-id";=0A= + reg =3D <0x0 0x4>;=0A= + };=0A= +=0A= + interrupt-controller@1b0 {=0A= + compatible =3D "aspeed,ast2700-scu-ic0";=0A= + reg =3D <0x1b0 0x4>;=0A= + #interrupt-cells =3D <1>;=0A= + interrupts-extended =3D <&intc0 97>;=0A= + interrupt-controller;=0A= + };=0A= +=0A= + interrupt-controller@1e0 {=0A= + compatible =3D "aspeed,ast2700-scu-ic1";=0A= + reg =3D <0x1e0 0x4>;=0A= + #interrupt-cells =3D <1>;=0A= + interrupts-extended =3D <&intc0 98>;=0A= + interrupt-controller;=0A= + };=0A= +=0A= + pinctrl@400 {=0A= + compatible =3D "aspeed,ast2700-soc0-pinctrl";=0A= + reg =3D <0x400 0x318>;=0A= + emmc-state {=0A= + function =3D "EMMC";=0A= + groups =3D "EMMCG1";=0A= + };=0A= + };=0A= + };=0A= + };=0A= + };=0A= +=0A= ...=0A= =0A= One additional question regarding the example: Since the AST2700 SCU0=0A= node is not significantly different from previous generations and the=0A= example mostly uses standard properties, do you think keeping this=0A= additional example is useful, or would you prefer to keep the binding=0A= minimal?=0A= =0A= Thanks=0A= Billy Tsai=0A=