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bh=DWM2os22LUr8ZhDKf2g2SFoPx1FREyLA+mCLN34Nhew=; b=ijmaS/GSM+PYgfurlfBo95qlhhECv2pyJIHuScw3Os7Qr1k764NPxumXRJIgofKAjVpDmGkU2j7NNXCSD/W7cPXhaiP/PeptuhTWsaGE13GstF9IpiV9m+7q08uH/EFroKkfdnrGRwsnOFszJawDLGoHTAutQj6JRPx/7SqzNF4paL9NSELurV9vL9b2J19iqhsV6J2IcXMHIaYKn3QSlpXTh8h5oqW6GUWtZ/IkUtskLcL0aWEKjp5ZQkpzA6LWDOK3AD3l2UL7ojBoQK0T7lVmGmfHuSD/WFYW2IqrUJ6PHZM5HJm8tOfhorYjQze6KeyTBpe/oOV4W7o5S6a1KA== Received: from OSQPR06MB7252.apcprd06.prod.outlook.com (2603:1096:604:29c::6) by TYSPR06MB6765.apcprd06.prod.outlook.com (2603:1096:400:476::13) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9298.16; Tue, 11 Nov 2025 02:24:02 +0000 Received: from OSQPR06MB7252.apcprd06.prod.outlook.com ([fe80::814e:819a:7d52:7448]) by OSQPR06MB7252.apcprd06.prod.outlook.com ([fe80::814e:819a:7d52:7448%3]) with mapi id 15.20.9298.015; Tue, 11 Nov 2025 02:24:02 +0000 From: Billy Tsai To: Andrew Jeffery , "lee@kernel.org" , "robh@kernel.org" , "krzk+dt@kernel.org" , "conor+dt@kernel.org" , "joel@jms.id.au" , "linus.walleij@linaro.org" , "brgl@bgdev.pl" , "devicetree@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-aspeed@lists.ozlabs.org" , "linux-kernel@vger.kernel.org" , "openbmc@lists.ozlabs.org" , "linux-gpio@vger.kernel.org" , BMC-SW Subject: Re: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support Thread-Topic: [PATCH v2 3/4] pinctrl: aspeed: Add AST2700 pinmux support Thread-Index: AQHcHYd18lbI5El9VE2aAexfEXfel7SjdDmAgBMm8Co= Date: Tue, 11 Nov 2025 02:24:02 +0000 Message-ID: References: <20250904103401.88287-1-billy_tsai@aspeedtech.com> <20250904103401.88287-4-billy_tsai@aspeedtech.com> <005c9928cde01c8a3bf4840692eddf13f2c08282.camel@codeconstruct.com.au> In-Reply-To: <005c9928cde01c8a3bf4840692eddf13f2c08282.camel@codeconstruct.com.au> Accept-Language: en-US, zh-TW Content-Language: en-US X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: authentication-results: dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=aspeedtech.com; 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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSQPR06MB7252.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 388946a2-faa0-4056-1da8-08de20c9613b X-MS-Exchange-CrossTenant-originalarrivaltime: 11 Nov 2025 02:24:02.4782 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: FL1pHugqAtRllA97+U8aXs9qJdp3YIfqrTPslpIFbQhof28PyD3DfhIlDjFrf3i64ox94HIsF8mKEq+ZBaP8TbbFC+MxWdLElznOuWilykk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: TYSPR06MB6765 > >=A0This patch adds pinmux support for=A0the AST2700, which includes two = SoC=0A= > >=A0configurations:=0A= > > -=A0SoC0 closely resembles previous generations of ASPEED BMC SoCs, all= owing=0A= > >=A0the reuse of existing macros and callback functions.=0A= > > -=A0SoC1, however, introduces a new logic for=A0configuring pin functio= ns.=0A= > >=A0Therefore, new g7_set_mux and gpio_request_enable functions are=0A= > >=A0implemented to properly configure the pinctrl registers using the=0A= > >=A0pin_cfg table and to resolve GPIO request errors.=0A= =A0=0A= >=A0Do you mind splitting support for=A0soc0 and soc1 into separate patches= ?=0A= >=A0Having taken a brief look I think we're also due for some further=0A= > separation of the code. Particularly, isolating the patch for soc0=0A= > would be nice, as the register design for soc1 is just _so_ much nicer,= =0A= > and I'd like to avoid dragging the baggage of previous generations=0A= >=A0along with it.=0A= =A0=0A= Okay, I will split the support for=A0SoC0 and SoC1 into separate patches.= =0A= SoC0 will follow the existing design closely, while=A0SoC1 will introduce= =0A= a new logic for=A0configuring pin functions.=0A= =A0=0A= > >=0A= > >=A0The driver supports:=0A= > > -=A0All 12=A0GPIO-capable pins in SoC0=0A= > > -=A0All 212=A0GPIO-capable pins in SoC1=0A= > >=0A= > >=A0Additionally, this patch introduces several pseudo-ball definitions f= or=0A= > >=A0specific configuration purposes:=0A= > > -=A0USB function selection=0A= > > -=A0JTAG target selection=0A= > > -=A0PCIe RC PERST configuration=0A= > > -=A0SGMII PHY selection=0A= > >=0A= > >=A0Signed-off-by: Billy Tsai =0A= > > ---=0A= > >=A0drivers/pinctrl/aspeed/Kconfig | 8 +=0A= > >=A0drivers/pinctrl/aspeed/Makefile | 1 +=0A= > >=A0.../pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c | 503 ++++=0A= > >=A0.../pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c | 2523 +++++++++++++++++= =0A= > >=A0drivers/pinctrl/aspeed/pinctrl-aspeed.c | 47 +=0A= > >=A0drivers/pinctrl/aspeed/pinctrl-aspeed.h | 11 +-=0A= > >=A0drivers/pinctrl/aspeed/pinmux-aspeed.h | 35 +-=0A= =A0=0A= >=A0The impression I get from the changes to the latter three files here is= =0A= >=A0that the soc0 support might even be different enough to warrant=0A= >=A0separation from the previous generations as well. You're defining=0A= > similar-but-different structs and macros to what we already have. If=0A= > the those are genuinely necessary (not yet resolved), I'd rather they=0A= >=A0be their own driver.=0A= =A0=0A= Understood. I will modify the patch of the SoC0 to meet the concept with pr= evious=0A= generations. If the differences are significant, I will consider creating a= =0A= separate driver for=A0it. But, at this moment, I believe the existing drive= r and=A0macro can=0A= be adapted to support SoC0 with minimal changes.=0A= =A0=0A= > > 7=A0files changed, 3123 insertions(+), 5 deletions(-)=0A= > >=A0create mode 100644=A0drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c= =0A= > >=A0create mode 100644=A0drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c= =0A= > >=0A= > >=A0diff --git a/drivers/pinctrl/aspeed/Kconfig b/drivers/pinctrl/aspeed/= Kconfig=0A= > >=A0index 1a4e5b9ed471..16743091a139 100644=0A= > > ---=A0a/drivers/pinctrl/aspeed/Kconfig=0A= > > +++=A0b/drivers/pinctrl/aspeed/Kconfig=0A= > >=A0@@ -31,3 +31,11=A0@@ config PINCTRL_ASPEED_G6=0A= > >=A0help=0A= > >=A0Say Y here to enable pin controller support for=A0Aspeed's 6th=0A= > > generation SoCs. GPIO is provided by a separate GPIO driver.=0A= > > +=0A= > > +config PINCTRL_ASPEED_G7=0A= > > + bool "Aspeed G7 SoC pin control"=0A= > > + depends on (ARCH_ASPEED || COMPILE_TEST) && OF=0A= > > + select PINCTRL_ASPEED=0A= > > + help=0A= > > + Say Y here to enable pin controller support for Aspeed's 7th=0A= > > +=A0generation SoCs. GPIO is provided by a separate GPIO driver.=0A= > >=A0diff --git a/drivers/pinctrl/aspeed/Makefile b/drivers/pinctrl/aspeed= /Makefile=0A= > >=A0index db2a7600ae2b..1713f678a984 100644=0A= > > ---=A0a/drivers/pinctrl/aspeed/Makefile=0A= > > +++=A0b/drivers/pinctrl/aspeed/Makefile=0A= > >=A0@@ -6,3 +6,4=A0@@ obj-$(CONFIG_PINCTRL_ASPEED) +=3D=A0pinctrl-aspeed.= o pinmux-aspeed.o=0A= > >=A0obj-$(CONFIG_PINCTRL_ASPEED_G4) +=3D=A0pinctrl-aspeed-g4.o=0A= > >=A0obj-$(CONFIG_PINCTRL_ASPEED_G5) +=3D=A0pinctrl-aspeed-g5.o=0A= > >=A0obj-$(CONFIG_PINCTRL_ASPEED_G6) +=3D=A0pinctrl-aspeed-g6.o=0A= > > +obj-$(CONFIG_PINCTRL_ASPEED_G7) +=3D=A0pinctrl-aspeed-g7-soc0.o pinctr= l-aspeed-g7-soc1.o=0A= > >=A0\ No newline at end of file=0A= > >=A0diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c b/driver= s/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c=0A= > >=A0new file mode 100644=0A= > >=A0index 000000000000..86da889cc010=0A= > > --- /dev/null=0A= > > +++=A0b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc0.c=0A= > >=A0@@ -0,0 +1,503=A0@@=0A= > > +// SPDX-License-Identifier: GPL-2.0=0A= > > +=0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include =0A= > > +#include "pinctrl-aspeed.h"=0A= > > +#include "../pinctrl-utils.h"=0A= > > +=0A= > > +#define SCU200 0x200=A0/* System Reset Control #1 */=0A= > > +=0A= > > +#define SCU400 0x400=A0/* Multi-function Pin Control #1 */=0A= > > +#define SCU404 0x404=A0/* Multi-function Pin Control #2 */=0A= > > +#define SCU408 0x408=A0/* Multi-function Pin Control #3 */=0A= > > +#define SCU40C 0x40C=A0/* Multi-function Pin Control #3 */=0A= > > +#define SCU410 0x410=A0/* USB Multi-function Control Register */=0A= > > +#define SCU414 0x414=A0/* VGA Function Control Register */=0A= > > +=0A= > > +#define SCU480 0x480=A0/* GPIO18A0 IO Control Register */=0A= > > +#define SCU484 0x484=A0/* GPIO18A1 IO Control Register */=0A= > > +#define SCU488 0x488=A0/* GPIO18A2 IO Control Register */=0A= > > +#define SCU48C 0x48c=A0/* GPIO18A3 IO Control Register */=0A= > > +#define SCU490 0x490=A0/* GPIO18A4 IO Control Register */=0A= > > +#define SCU494 0x494=A0/* GPIO18A5 IO Control Register */=0A= > > +#define SCU498 0x498=A0/* GPIO18A6 IO Control Register */=0A= > > +#define SCU49C 0x49c=A0/* GPIO18A7 IO Control Register */=0A= > > +#define SCU4A0 0x4A0=A0/* GPIO18B0 IO Control Register */=0A= > > +#define SCU4A4 0x4A4=A0/* GPIO18B1 IO Control Register */=0A= > > +#define SCU4A8 0x4A8=A0/* GPIO18B2 IO Control Register */=0A= > > +#define SCU4AC 0x4AC=A0/* GPIO18B3 IO Control Register */=0A= > > +=0A= > > +enum=A0{=0A= > > +=A0AC14,=0A= > > +=A0AE15,=0A= =A0=0A= >=A0Are the ball enums necessary?=A0Historically we haven't needed it as th= e=0A= > undefined macro symbols were just used for token-pasting or=0A= > stringification purposes.=0A= =A0=0A= The enums are used to replace the #define M24 0, #define M25 1, =85 definit= ions in=0A= the G6 pinctrl driver. Additionally, the number assigned to each ball name = must=0A= follow the sequence of GPIO numbering. In other words, the number assigned = to each=0A= ball name is meaningful, and the order should not be changed. Therefore, I = believe=0A= that using enums is a better approach than using #define macros.=0A= =A0=0A= > > + AD14,=0A= > > + AE14,=0A= > > + AF14,=0A= > > + AB13,=0A= > > + AB14,=0A= > > + AF15,=0A= > > + AF13,=0A= > > + AC13,=0A= > > + AD13,=0A= > > + AE13,=0A= > > + PORTA_U3, // SCU410[1:0]=0A= > > + PORTA_U2, // SCU410[3:2]=0A= > > + PORTB_U3, // SCU410[5:4]=0A= > > + PORTB_U2, // SCU410[7:6]=0A= > > + PORTA_U3_XHCI, // SCU410[9]=0A= > > + PORTA_U2_XHCI, // SCU410[9]=0A= > > + PORTB_U3_XHCI, // SCU410[10]=0A= > > + PORTB_U2_XHCI, // SCU410[10]=0A= > > + PORTA_MODE, // SCU410[25:24]=0A= > > + PORTB_MODE, // SCU410[29:28]=0A= > > + PORTA_U2_PHY,=0A= > > + PORTA_U3_PHY,=0A= > > + PORTB_U2_PHY,=0A= > > + PORTB_U3_PHY,=0A= > > + JTAG_PORT,=0A= > > + PCIERC0_PERST,=0A= > > + PCIERC1_PERST,=0A= > > +};=0A= > > +=0A= > > +GROUP_DECL(EMMCG1, AC14, AE15, AD14);=0A= > > +GROUP_DECL(EMMCG4, AC14, AE15, AD14, AE14, AF14, AB13);=0A= > > +GROUP_DECL(EMMCG8, AC14, AE15, AD14, AE14, AF14, AB13, AF13, AC13, AD1= 3, AE13);=0A= > > +GROUP_DECL(EMMCWPN, AF15);=0A= > > +GROUP_DECL(EMMCCDN, AB14);=0A= > > +GROUP_DECL(VGADDC, AD13, AE13);=0A= > > +GROUP_DECL(VB1, AC14, AE15, AD14, AE14);=0A= > > +GROUP_DECL(VB0, AF15, AB14, AF13, AC13);=0A= =A0=0A= > For the previous generation drivers my philosophy was "keep things that= =0A= > go together together," so signal descriptors, groups and functions were= =0A= > all located around the definition for one or a set of balls.=0A= =A0=0A= > Given I'm potentially escaping maintenance of ASPEED pinctrl drivers=0A= > for=A0the 2700=A0onwards I won't complain too much, but was this a specif= ic=0A= > choice to break from that approach? You're defining all the groups,=0A= >=A0then all the functions, then all the configurations.=0A= =A0=0A= The groups and the functions can be put together, but the ball define=0A= as the above reasons. So, I will keep the ball defines at the top with the = enums.=0A= =A0=0A= > >=A0diff --git a/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c b/driver= s/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c=0A= > >=A0new file mode 100644=0A= > >=A0index 000000000000..7c5a5e208f63=0A= > > --- /dev/null=0A= > > +++=A0b/drivers/pinctrl/aspeed/pinctrl-aspeed-g7-soc1.c=0A= > >=0A= =A0=0A= > *snip*=0A= =A0=0A= > > +=0A= > > +FUNCFG_DESCL(C16, PIN_CFG(ESPI1, SCU400, GENMASK(2, 0), 1),=0A= > > + PIN_CFG(LPC1, SCU400, GENMASK(2, 0), 2),=0A= > > + PIN_CFG(SD, SCU400, GENMASK(2, 0), 3),=0A= > > + PIN_CFG(DI2C0, SCU400, GENMASK(2, 0), 4),=0A= > > + PIN_CFG(VPI, SCU400, GENMASK(2, 0), 5));=0A= > > +FUNCFG_DESCL(C14, PIN_CFG(ESPI1, SCU400, GENMASK(6, 4), (1 << 4)),=0A= > > + PIN_CFG(LPC1, SCU400, GENMASK(6, 4), (2 << 4)),=0A= > > + PIN_CFG(SD, SCU400, GENMASK(6, 4), (3 << 4)),=0A= > > + PIN_CFG(DI2C1, SCU400, GENMASK(6, 4), (4 << 4)),=0A= > > + PIN_CFG(VPI, SCU400, GENMASK(6, 4), (5 << 4)));=0A= > > +FUNCFG_DESCL(C11, PIN_CFG(ESPI1, SCU400, GENMASK(10, 8), (1 << 8)),=0A= > > + PIN_CFG(LPC1, SCU400, GENMASK(10, 8), (2 << 8)),=0A= > > + PIN_CFG(SD, SCU400, GENMASK(10, 8), (3 << 8)),=0A= > > + PIN_CFG(DI2C3, SCU400, GENMASK(10, 8), (4 << 8)),=0A= > > + PIN_CFG(VPI, SCU400, GENMASK(10, 8), (5 << 8)));=0A= =A0=0A= >=A0If we're going to continue the macro soup we need to take the=0A= > opportunity to clean this up. You shouldn't need to open-code the=0A= >=A0shifts like this, the data model needs more thought.=0A= =A0=0A= Got it. I will improve the macros to avoid open-coding shifts.=0A= =A0=0A= > > +=0A= > > +static const struct=A0aspeed_g7_pincfg pin_cfg[] =3D=A0{=0A= > > + PINCFG_PIN(C16), PINCFG_PIN(C14), PINCFG_PIN(C11),=0A= > > + PINCFG_PIN(D9), PINCFG_PIN(F14), PINCFG_PIN(D10),=0A= =A0=0A= >=A0My preference is that this array definition be one entry per line,=0A= >=A0sorted, that way we don't get weird alignment or reflow affecting the= =0A= > remainder of the struct if we change things in the middle.=0A= =A0=0A= Okay, I will format the array definition to have one entry per line and sor= ted.=0A= =A0=0A= Thanks=0A= =A0=0A= Best regards,=0A= Billy Tsai=