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charset="Windows-1252" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: aspeedtech.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSQPR06MB7252.apcprd06.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 0084dea0-6ecb-415b-b018-08dce80a04af X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Oct 2024 02:28:10.5696 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: 43d4aa98-e35b-4575-8939-080e90d5a249 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2j8A3SPFiEb9zRXPUz2rQalhxcwuJxWXQDgci6kN3dSbEyV+orEsNqbr1tHvNllA2LcCYZX9MMII4et/kX0xgWKp+pzRF+RnwtKCPxPHutU= X-MS-Exchange-Transport-CrossTenantHeadersStamped: SEZPR06MB5543 > > In the 7th generation of the SoC from Aspeed, the control logic of the= =0A= > > GPIO controller has been updated to support per-pin control. Each pin n= ow=0A= > > has its own 32-bit register, allowing for individual control of the pin= 's=0A= > > value, direction, interrupt type, and other settings. The permission fo= r=0A= > > coprocessor access is supported by the hardware but hasn't been=0A= > > implemented in the current patch.=0A= > >=0A= > > Signed-off-by: Billy Tsai =0A= > > ---=0A= > > drivers/gpio/gpio-aspeed.c | 147 +++++++++++++++++++++++++++++++++++++= =0A= > > 1 file changed, 147 insertions(+)=0A= > >=0A= > > diff --git a/drivers/gpio/gpio-aspeed.c b/drivers/gpio/gpio-aspeed.c=0A= > > index 5d583cc9cbc7..208f95fb585e 100644=0A= > > --- a/drivers/gpio/gpio-aspeed.c=0A= > > +++ b/drivers/gpio/gpio-aspeed.c=0A= > > @@ -30,6 +30,27 @@=0A= > > #include =0A= > > #include "gpiolib.h"=0A= > >=0A= > > +/* Non-constant mask variant of FIELD_GET() and FIELD_PREP() */=0A= > > +#define field_get(_mask, _reg) (((_reg) & (_mask)) >> (ffs(_mask= ) - 1))=0A= > > +#define field_prep(_mask, _val) (((_val) << (ffs(_mask) - 1)) & (= _mask))=0A= > > +=0A= > > +#define GPIO_G7_IRQ_STS_BASE 0x100=0A= > > +#define GPIO_G7_IRQ_STS_OFFSET(x) (GPIO_G7_IRQ_STS_BASE + (x) * 0x4)= =0A= > > +#define GPIO_G7_CTRL_REG_BASE 0x180=0A= > > +#define GPIO_G7_CTRL_REG_OFFSET(x) (GPIO_G7_CTRL_REG_BASE + (x) * 0x4)= =0A= > > +#define GPIO_G7_CTRL_OUT_DATA BIT(0)=0A= > > +#define GPIO_G7_CTRL_DIR BIT(1)=0A= > > +#define GPIO_G7_CTRL_IRQ_EN BIT(2)=0A= > > +#define GPIO_G7_CTRL_IRQ_TYPE0 BIT(3)=0A= > > +#define GPIO_G7_CTRL_IRQ_TYPE1 BIT(4)=0A= > > +#define GPIO_G7_CTRL_IRQ_TYPE2 BIT(5)=0A= > > +#define GPIO_G7_CTRL_RST_TOLERANCE BIT(6)=0A= > > +#define GPIO_G7_CTRL_DEBOUNCE_SEL1 BIT(7)=0A= > > +#define GPIO_G7_CTRL_DEBOUNCE_SEL2 BIT(8)=0A= > > +#define GPIO_G7_CTRL_INPUT_MASK BIT(9)=0A= > > +#define GPIO_G7_CTRL_IRQ_STS BIT(12)=0A= > > +#define GPIO_G7_CTRL_IN_DATA BIT(13)=0A= > > +=0A= > > struct aspeed_bank_props {=0A= > > unsigned int bank;=0A= > > u32 input;=0A= > > @@ -95,6 +116,22 @@ struct aspeed_gpio_bank {=0A= > > */=0A= > >=0A= > > static const int debounce_timers[4] =3D { 0x00, 0x50, 0x54, 0x58 };=0A= > > +static const int g7_debounce_timers[4] =3D { 0x00, 0x00, 0x04, 0x08 };= =0A= > > +=0A= > > +/*=0A= > > + * The debounce timers array is used to configure the debounce timer s= ettings.Here=92s how it works:=0A= > > + * Array Value: Indicates the offset for configuring the debounce time= r.=0A= > > + * Array Index: Corresponds to the debounce setting register.=0A= > > + * The debounce timers array follows this pattern for configuring the = debounce setting registers:=0A= > > + * Array Index 0: No debounce timer is set;=0A= > > + * Array Value is irrelevant (don=92t care).=0A= > > + * Array Index 1: Debounce setting #2 is set to 1, and debounce settin= g #1 is set to 0.=0A= > > + * Array Value: offset for configuring debounce timer 0 (g= 4: 0x50, g7: 0x00)=0A= > > + * Array Index 2: Debounce setting #2 is set to 0, and debounce settin= g #1 is set to 1.=0A= > > + * Array Value: offset for configuring debounce timer 1 (g= 4: 0x54, g7: 0x04)=0A= > > + * Array Index 3: Debounce setting #2 is set to 1, and debounce settin= g #1 is set to 1.=0A= > > + * Array Value: offset for configuring debounce timer 2 (g= 4: 0x58, g7: 0x8)=0A= > > + */=0A= > >=0A= > > static const struct aspeed_gpio_copro_ops *copro_ops;=0A= > > static void *copro_data;=0A= > > @@ -250,6 +287,39 @@ static void __iomem *aspeed_gpio_g4_bank_reg(struc= t aspeed_gpio *gpio,=0A= > > BUG();=0A= > > }=0A= > >=0A= > > +static u32 aspeed_gpio_g7_reg_mask(const enum aspeed_gpio_reg reg)=0A= > > +{=0A= > > + switch (reg) {=0A= > > + case reg_val:=0A= > > + return GPIO_G7_CTRL_OUT_DATA;=0A= =0A= > I think a problem is that we want this to be GPIO_G7_CTRL_IN_DATA for=0A= > reads, but GPIO_G7_CTRL_OUT_DATA for writes?=0A= =0A= Yes. So in my aspeed_g7_bit_get, I will change the mask to GPIO_G7_CTRL_IN_= DATA.=0A= =0A= +static bool aspeed_g7_reg_bit_get(struct aspeed_gpio *gpio, unsigned int o= ffset,=0A= + const enum aspeed_gpio_reg reg)=0A= +{=0A= + u32 mask =3D aspeed_gpio_g7_reg_mask(reg);=0A= + void __iomem *addr;=0A= +=0A= + addr =3D gpio->base + GPIO_G7_CTRL_REG_OFFSET(offset);=0A= + if (reg =3D=3D reg_val)=0A= + mask =3D GPIO_G7_CTRL_IN_DATA;=0A= +=0A= + if (mask)=0A= + return field_get(mask, ioread32(addr));=0A= + else=0A= + return 0;=0A= +}=0A= +=