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Tue, 9 Sep 2025 07:30:44 +0000 From: "Shaopeng Tan (Fujitsu)" To: 'James Morse' , "linux-kernel@vger.kernel.org" , "linux-arm-kernel@lists.infradead.org" , "linux-acpi@vger.kernel.org" , "devicetree@vger.kernel.org" CC: "shameerali.kolothum.thodi@huawei.com" , D Scott Phillips OS , "carl@os.amperecomputing.com" , "lcherian@marvell.com" , "bobo.shaobowang@huawei.com" , "baolin.wang@linux.alibaba.com" , Jamie Iles , Xin Hao , "peternewman@google.com" , "dfustini@baylibre.com" , "amitsinght@marvell.com" , David Hildenbrand , Rex Nie , Dave Martin , Koba Ko , Shanker Donthineni , "fenghuay@nvidia.com" , "baisheng.gao@unisoc.com" , Jonathan Cameron , Rob Herring , Rohit Mathew , Rafael Wysocki , Len Brown , Lorenzo Pieralisi , Hanjun Guo , Sudeep Holla , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Greg Kroah-Hartman , Danilo Krummrich , Ben Horgan Subject: RE: [PATCH 12/33] arm_mpam: Add the class and component structures for ris firmware described Thread-Topic: [PATCH 12/33] arm_mpam: Add the class and component structures for ris firmware described Thread-Index: AQHcE3pkkI69kPmfV0CsLeBrNWtIprSKi/Ew Date: Tue, 9 Sep 2025 07:30:43 +0000 Message-ID: References: <20250822153048.2287-1-james.morse@arm.com> <20250822153048.2287-47-james.morse@arm.com> In-Reply-To: <20250822153048.2287-47-james.morse@arm.com> Accept-Language: ja-JP, en-US Content-Language: ja-JP X-MS-Has-Attach: X-MS-TNEF-Correlator: msip_labels: MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_ActionId=26406b4b-819a-4c93-ab81-7f321d6f7a58;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_ContentBits=0;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_Enabled=true;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_Method=Standard;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_Name=FUJITSU-RESTRICTED?;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_SetDate=2025-09-09T07:14:58Z;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_SiteId=a19f121d-81e1-4858-a9d8-736e267fd4c7;MSIP_Label_a7295cc1-d279-42ac-ab4d-3b0f4fece050_Tag=10, 3, 0, 1; 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charset="iso-2022-jp" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-ExternalHop-MessageData-0: oTTt2Jr2lUgpc+d55AmOPP/JNNHrK2wyGGY9uxeZMX3Nt7po34x+JiWeXgSz+vyKqcEw1Xrgq/TOg1zHMwUiKQGuQLIiWty1Da5z73Ro7APscTQtAPlNvpbTKaIeuFt7DcyubgbIkqgj+Yyz8StdZbREMyWVgbm0R7puA9KgAo5LaKzFEZLDTIkrbLc6L5oQqyYnDa2VW+dBLMzStasjX+7SpsXbzBEXUeDzExqcJl8j7mPM/9dsiWuhB8n+Bm8B8wfZILTOHcU5pZJdXPC8FQOUV/nghNc4JveVTUoxaCGAThygU+g8agxkqc6LiIC/4c24f8RlxLMc11lVwVqGGuNnDHtxXhvImuQuGRpa9SrZd57IvkrGPELt1MG7OkWppiZUeARYRrrdZDLXkIeBhSDIPI0uCEkZ7qCtF2DME2DRJURNQBLImuo0tr9yfbXlpHkPh7Glg6S8pUNM3U/YOLklXZX1L3s3WmLkiG074QA305nfQRaZRk2BmEY5XPrA5c4gq3N73JKHfsCo2Jr0iKF1skHi7wOWdq2HI/TYNyF2amt5NdPYuYyeyJPx4rHBprP1ic1H3bKJowb7JbiwKHrBh8k4qpyZELUtLUjuRdM4+l0BikNqSXnAsArcTH/h X-OriginatorOrg: fujitsu.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: OSZPR01MB8798.jpnprd01.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: d2615bb4-5c84-44d0-9ccf-08ddef72c970 X-MS-Exchange-CrossTenant-originalarrivaltime: 09 Sep 2025 07:30:44.0792 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: a19f121d-81e1-4858-a9d8-736e267fd4c7 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 5Me7MBHzPBfqFp62eBn8llPsDviVQt6mBd0mjV84fnF6A2SIDe7sZJrGvEyP2GafQ1X+jwToFIZHvOceSWcIEi669QVhPP0pu3/ffZGqsYk= X-MS-Exchange-Transport-CrossTenantHeadersStamped: OSCPR01MB16166 Hello James, > An MSC is a container of resources, each identified by their RIS index. > Some RIS are described by firmware to provide their position in the syste= m. > Others are discovered when the driver probes the hardware. >=20 > To configure a resource it needs to be found by its class, e.g. 'L2'. > There are two kinds of grouping, a class is a set of components, which ar= e > visible to user-space as there are likely to be multiple instances of the= L2 cache. > (e.g. one per cluster or package) >=20 > struct mpam_components are a set of struct mpam_vmsc. A vMSC groups the > RIS in an MSC that control the same logical piece of hardware. (e.g. L2). > This is to allow hardware implementations where two controls are presente= d as > different RIS. Re-combining these RIS allows their feature bits to be or-= ed. This > structure is not visible outside mpam_devices.c >=20 > struct mpam_vmsc are then a set of struct mpam_msc_ris, which are not > visible as each L2 cache may be composed of individual slices which need = to > be configured the same as the hardware is not able to distribute the > configuration. >=20 > Add support for creating and destroying these structures. >=20 > A gfp is passed as the structures may need creating when a new RIS entry = is > discovered when probing the MSC. >=20 > CC: Ben Horgan > Signed-off-by: James Morse > --- > Changes since RFC: > * removed a pr_err() debug message that crept in. > --- > drivers/resctrl/mpam_devices.c | 488 > +++++++++++++++++++++++++++++++- > drivers/resctrl/mpam_internal.h | 91 ++++++ > include/linux/arm_mpam.h | 8 +- > 3 files changed, 574 insertions(+), 13 deletions(-) >=20 > diff --git a/drivers/resctrl/mpam_devices.c b/drivers/resctrl/mpam_device= s.c > index 71a1fb1a9c75..5baf2a8786fb 100644 > --- a/drivers/resctrl/mpam_devices.c > +++ b/drivers/resctrl/mpam_devices.c > @@ -20,7 +20,6 @@ > #include > #include > #include > -#include > #include >=20 > #include > @@ -35,11 +34,483 @@ > static DEFINE_MUTEX(mpam_list_lock); > static LIST_HEAD(mpam_all_msc); >=20 > -static struct srcu_struct mpam_srcu; > +struct srcu_struct mpam_srcu; >=20 > /* MPAM isn't available until all the MSC have been probed. */ static u= 32 > mpam_num_msc; >=20 > +/* > + * An MSC is a physical container for controls and monitors, each > +identified by > + * their RIS index. These share a base-address, interrupts and some > +MMIO > + * registers. A vMSC is a virtual container for RIS in an MSC that > +control or > + * monitor the same thing. Members of a vMSC are all RIS in the same > +MSC, but > + * not all RIS in an MSC share a vMSC. > + * Components are a group of vMSC that control or monitor the same > +thing but > + * are from different MSC, so have different base-address, interrupts et= c. > + * Classes are the set components of the same type. > + * > + * The features of a vMSC is the union of the RIS it contains. > + * The features of a Class and Component are the common subset of the > +vMSC > + * they contain. > + * > + * e.g. The system cache may have bandwidth controls on multiple > +interfaces, > + * for regulating traffic from devices independently of traffic from CPU= s. > + * If these are two RIS in one MSC, they will be treated as controlling > + * different things, and will not share a vMSC/component/class. > + * > + * e.g. The L2 may have one MSC and two RIS, one for cache-controls > +another > + * for bandwidth. These two RIS are members of the same vMSC. > + * > + * e.g. The set of RIS that make up the L2 are grouped as a component. > +These > + * are sometimes termed slices. They should be configured the same, as > +if there > + * were only one. > + * > + * e.g. The SoC probably has more than one L2, each attached to a > +distinct set > + * of CPUs. All the L2 components are grouped as a class. > + * > + * When creating an MSC, struct mpam_msc is added to the all > +mpam_all_msc list, > + * then linked via struct mpam_ris to a vmsc, component and class. > + * The same MSC may exist under different class->component->vmsc paths, > +but the > + * RIS index will be unique. > + */ > +LIST_HEAD(mpam_classes); > + > +/* List of all objects that can be free()d after synchronise_srcu() */ > +static LLIST_HEAD(mpam_garbage); > + > +#define init_garbage(x) init_llist_node(&(x)->garbage.llist) > + > +static struct mpam_vmsc * > +mpam_vmsc_alloc(struct mpam_component *comp, struct mpam_msc > *msc, > +gfp_t gfp) { > + struct mpam_vmsc *vmsc; > + > + lockdep_assert_held(&mpam_list_lock); > + > + vmsc =3D kzalloc(sizeof(*vmsc), gfp); > + if (!comp) > + return ERR_PTR(-ENOMEM); > + init_garbage(vmsc); > + > + INIT_LIST_HEAD_RCU(&vmsc->ris); > + INIT_LIST_HEAD_RCU(&vmsc->comp_list); > + vmsc->comp =3D comp; > + vmsc->msc =3D msc; > + > + list_add_rcu(&vmsc->comp_list, &comp->vmsc); > + > + return vmsc; > +} > + > +static struct mpam_vmsc *mpam_vmsc_get(struct mpam_component > *comp, > + struct mpam_msc *msc, bool alloc, > + gfp_t gfp) > +{ > + struct mpam_vmsc *vmsc; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_for_each_entry(vmsc, &comp->vmsc, comp_list) { > + if (vmsc->msc->id =3D=3D msc->id) > + return vmsc; > + } > + > + if (!alloc) > + return ERR_PTR(-ENOENT); It seems like it is always false here. If necessary, why not do this at the beginning of the function? > + return mpam_vmsc_alloc(comp, msc, gfp); } > + > +static struct mpam_component * > +mpam_component_alloc(struct mpam_class *class, int id, gfp_t gfp) { > + struct mpam_component *comp; > + > + lockdep_assert_held(&mpam_list_lock); > + > + comp =3D kzalloc(sizeof(*comp), gfp); > + if (!comp) > + return ERR_PTR(-ENOMEM); > + init_garbage(comp); > + > + comp->comp_id =3D id; > + INIT_LIST_HEAD_RCU(&comp->vmsc); > + /* affinity is updated when ris are added */ > + INIT_LIST_HEAD_RCU(&comp->class_list); > + comp->class =3D class; > + > + list_add_rcu(&comp->class_list, &class->components); > + > + return comp; > +} > + > +static struct mpam_component * > +mpam_component_get(struct mpam_class *class, int id, bool alloc, gfp_t > +gfp) { > + struct mpam_component *comp; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_for_each_entry(comp, &class->components, class_list) { > + if (comp->comp_id =3D=3D id) > + return comp; > + } > + > + if (!alloc) > + return ERR_PTR(-ENOENT); Same here. > + return mpam_component_alloc(class, id, gfp); } > + > +static struct mpam_class * > +mpam_class_alloc(u8 level_idx, enum mpam_class_types type, gfp_t gfp) { > + struct mpam_class *class; > + > + lockdep_assert_held(&mpam_list_lock); > + > + class =3D kzalloc(sizeof(*class), gfp); > + if (!class) > + return ERR_PTR(-ENOMEM); > + init_garbage(class); > + > + INIT_LIST_HEAD_RCU(&class->components); > + /* affinity is updated when ris are added */ > + class->level =3D level_idx; > + class->type =3D type; > + INIT_LIST_HEAD_RCU(&class->classes_list); > + > + list_add_rcu(&class->classes_list, &mpam_classes); > + > + return class; > +} > + > +static struct mpam_class * > +mpam_class_get(u8 level_idx, enum mpam_class_types type, bool alloc, > +gfp_t gfp) { > + bool found =3D false; > + struct mpam_class *class; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_for_each_entry(class, &mpam_classes, classes_list) { > + if (class->type =3D=3D type && class->level =3D=3D level_idx) { > + found =3D true; > + break; > + } > + } > + > + if (found) > + return class; > + > + if (!alloc) > + return ERR_PTR(-ENOENT); Same here. Best regards, Shaopeng TAN > + return mpam_class_alloc(level_idx, type, gfp); } > + > +#define add_to_garbage(x) \ > +do { \ > + __typeof__(x) _x =3D x; \ > + (_x)->garbage.to_free =3D (_x); \ > + llist_add(&(_x)->garbage.llist, &mpam_garbage); \ > +} while (0) > + > +static void mpam_class_destroy(struct mpam_class *class) { > + lockdep_assert_held(&mpam_list_lock); > + > + list_del_rcu(&class->classes_list); > + add_to_garbage(class); > +} > + > +static void mpam_comp_destroy(struct mpam_component *comp) { > + struct mpam_class *class =3D comp->class; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_del_rcu(&comp->class_list); > + add_to_garbage(comp); > + > + if (list_empty(&class->components)) > + mpam_class_destroy(class); > +} > + > +static void mpam_vmsc_destroy(struct mpam_vmsc *vmsc) { > + struct mpam_component *comp =3D vmsc->comp; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_del_rcu(&vmsc->comp_list); > + add_to_garbage(vmsc); > + > + if (list_empty(&comp->vmsc)) > + mpam_comp_destroy(comp); > +} > + > +static void mpam_ris_destroy(struct mpam_msc_ris *ris) { > + struct mpam_vmsc *vmsc =3D ris->vmsc; > + struct mpam_msc *msc =3D vmsc->msc; > + struct platform_device *pdev =3D msc->pdev; > + struct mpam_component *comp =3D vmsc->comp; > + struct mpam_class *class =3D comp->class; > + > + lockdep_assert_held(&mpam_list_lock); > + > + cpumask_andnot(&comp->affinity, &comp->affinity, &ris->affinity); > + cpumask_andnot(&class->affinity, &class->affinity, &ris->affinity); > + clear_bit(ris->ris_idx, msc->ris_idxs); > + list_del_rcu(&ris->vmsc_list); > + list_del_rcu(&ris->msc_list); > + add_to_garbage(ris); > + ris->garbage.pdev =3D pdev; > + > + if (list_empty(&vmsc->ris)) > + mpam_vmsc_destroy(vmsc); > +} > + > +/* > + * There are two ways of reaching a struct mpam_msc_ris. Via the > + * class->component->vmsc->ris, or via the msc. > + * When destroying the msc, the other side needs unlinking and cleaning = up > too. > + */ > +static void mpam_msc_destroy(struct mpam_msc *msc) { > + struct platform_device *pdev =3D msc->pdev; > + struct mpam_msc_ris *ris, *tmp; > + > + lockdep_assert_held(&mpam_list_lock); > + > + list_del_rcu(&msc->glbl_list); > + platform_set_drvdata(pdev, NULL); > + > + list_for_each_entry_safe(ris, tmp, &msc->ris, msc_list) > + mpam_ris_destroy(ris); > + > + add_to_garbage(msc); > + msc->garbage.pdev =3D pdev; > +} > + > +static void mpam_free_garbage(void) > +{ > + struct mpam_garbage *iter, *tmp; > + struct llist_node *to_free =3D llist_del_all(&mpam_garbage); > + > + if (!to_free) > + return; > + > + synchronize_srcu(&mpam_srcu); > + > + llist_for_each_entry_safe(iter, tmp, to_free, llist) { > + if (iter->pdev) > + devm_kfree(&iter->pdev->dev, iter->to_free); > + else > + kfree(iter->to_free); > + } > +} > + > +/* Called recursively to walk the list of caches from a particular CPU > +*/ static void __mpam_get_cpumask_from_cache_id(int cpu, struct > device_node *cache_node, > + unsigned long cache_id, > + u32 cache_level, > + cpumask_t *affinity) > +{ > + int err; > + u32 iter_level; > + unsigned long iter_cache_id; > + struct device_node *iter_node __free(device_node) =3D > +of_find_next_cache_node(cache_node); > + > + if (!iter_node) > + return; > + > + err =3D of_property_read_u32(iter_node, "cache-level", &iter_level); > + if (err) > + return; > + > + /* > + * get_cpu_cacheinfo_id() isn't ready until sometime > + * during device_initcall(). Use cache_of_calculate_id(). > + */ > + iter_cache_id =3D cache_of_calculate_id(iter_node); > + if (cache_id =3D=3D ~0UL) > + return; > + > + if (iter_level =3D=3D cache_level && iter_cache_id =3D=3D cache_id) > + cpumask_set_cpu(cpu, affinity); > + > + __mpam_get_cpumask_from_cache_id(cpu, iter_node, cache_id, > cache_level, > + affinity); > +} > + > +/* > + * The cacheinfo structures are only populated when CPUs are online. > + * This helper walks the device tree to include offline CPUs too. > + */ > +int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 > cache_level, > + cpumask_t *affinity) > +{ > + int cpu; > + > + if (!acpi_disabled) > + return acpi_pptt_get_cpumask_from_cache_id(cache_id, > affinity); > + > + for_each_possible_cpu(cpu) { > + struct device_node *cpu_node __free(device_node) =3D > of_get_cpu_node(cpu, NULL); > + if (!cpu_node) { > + pr_err("Failed to find cpu%d device node\n", cpu); > + return -ENOENT; > + } > + > + __mpam_get_cpumask_from_cache_id(cpu, cpu_node, > cache_id, > + cache_level, affinity); > + continue; > + } > + > + return 0; > +} > + > +/* > + * cpumask_of_node() only knows about online CPUs. This can't tell us > +whether > + * a class is represented on all possible CPUs. > + */ > +static void get_cpumask_from_node_id(u32 node_id, cpumask_t *affinity) > +{ > + int cpu; > + > + for_each_possible_cpu(cpu) { > + if (node_id =3D=3D cpu_to_node(cpu)) > + cpumask_set_cpu(cpu, affinity); > + } > +} > + > +static int get_cpumask_from_cache(struct device_node *cache, > + cpumask_t *affinity) > +{ > + int err; > + u32 cache_level; > + unsigned long cache_id; > + > + err =3D of_property_read_u32(cache, "cache-level", &cache_level); > + if (err) { > + pr_err("Failed to read cache-level from cache node\n"); > + return -ENOENT; > + } > + > + cache_id =3D cache_of_calculate_id(cache); > + if (cache_id =3D=3D ~0UL) { > + pr_err("Failed to calculate cache-id from cache node\n"); > + return -ENOENT; > + } > + > + return mpam_get_cpumask_from_cache_id(cache_id, cache_level, > +affinity); } > + > +static int mpam_ris_get_affinity(struct mpam_msc *msc, cpumask_t > *affinity, > + enum mpam_class_types type, > + struct mpam_class *class, > + struct mpam_component *comp) > +{ > + int err; > + > + switch (type) { > + case MPAM_CLASS_CACHE: > + err =3D mpam_get_cpumask_from_cache_id(comp->comp_id, > class->level, > + affinity); > + if (err) > + return err; > + > + if (cpumask_empty(affinity)) > + pr_warn_once("%s no CPUs associated with cache > node", > + dev_name(&msc->pdev->dev)); > + > + break; > + case MPAM_CLASS_MEMORY: > + get_cpumask_from_node_id(comp->comp_id, affinity); > + /* affinity may be empty for CPU-less memory nodes */ > + break; > + case MPAM_CLASS_UNKNOWN: > + return 0; > + } > + > + cpumask_and(affinity, affinity, &msc->accessibility); > + > + return 0; > +} > + > +static int mpam_ris_create_locked(struct mpam_msc *msc, u8 ris_idx, > + enum mpam_class_types type, u8 > class_id, > + int component_id, gfp_t gfp) > +{ > + int err; > + struct mpam_vmsc *vmsc; > + struct mpam_msc_ris *ris; > + struct mpam_class *class; > + struct mpam_component *comp; > + > + lockdep_assert_held(&mpam_list_lock); > + > + if (test_and_set_bit(ris_idx, msc->ris_idxs)) > + return -EBUSY; > + > + ris =3D devm_kzalloc(&msc->pdev->dev, sizeof(*ris), gfp); > + if (!ris) > + return -ENOMEM; > + init_garbage(ris); > + > + class =3D mpam_class_get(class_id, type, true, gfp); > + if (IS_ERR(class)) > + return PTR_ERR(class); > + > + comp =3D mpam_component_get(class, component_id, true, gfp); > + if (IS_ERR(comp)) { > + if (list_empty(&class->components)) > + mpam_class_destroy(class); > + return PTR_ERR(comp); > + } > + > + vmsc =3D mpam_vmsc_get(comp, msc, true, gfp); > + if (IS_ERR(vmsc)) { > + if (list_empty(&comp->vmsc)) > + mpam_comp_destroy(comp); > + return PTR_ERR(vmsc); > + } > + > + err =3D mpam_ris_get_affinity(msc, &ris->affinity, type, class, comp); > + if (err) { > + if (list_empty(&vmsc->ris)) > + mpam_vmsc_destroy(vmsc); > + return err; > + } > + > + ris->ris_idx =3D ris_idx; > + INIT_LIST_HEAD_RCU(&ris->vmsc_list); > + ris->vmsc =3D vmsc; > + > + cpumask_or(&comp->affinity, &comp->affinity, &ris->affinity); > + cpumask_or(&class->affinity, &class->affinity, &ris->affinity); > + list_add_rcu(&ris->vmsc_list, &vmsc->ris); > + > + return 0; > +} > + > +int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, > + enum mpam_class_types type, u8 class_id, int > component_id) { > + int err; > + > + mutex_lock(&mpam_list_lock); > + err =3D mpam_ris_create_locked(msc, ris_idx, type, class_id, > + component_id, GFP_KERNEL); > + mutex_unlock(&mpam_list_lock); > + if (err) > + mpam_free_garbage(); > + > + return err; > +} > + > static void mpam_discovery_complete(void) { > pr_err("Discovered all MSC\n"); > @@ -179,7 +650,10 @@ static int update_msc_accessibility(struct mpam_msc > *msc) > cpumask_copy(&msc->accessibility, cpu_possible_mask); > err =3D 0; > } else { > - if (of_device_is_compatible(parent, "memory")) { > + if (of_device_is_compatible(parent, "cache")) { > + err =3D get_cpumask_from_cache(parent, > + &msc->accessibility); > + } else if (of_device_is_compatible(parent, "memory")) { > cpumask_copy(&msc->accessibility, > cpu_possible_mask); > err =3D 0; > } else { > @@ -209,11 +683,10 @@ static void mpam_msc_drv_remove(struct > platform_device *pdev) >=20 > mutex_lock(&mpam_list_lock); > mpam_num_msc--; > - platform_set_drvdata(pdev, NULL); > - list_del_rcu(&msc->glbl_list); > - synchronize_srcu(&mpam_srcu); > - devm_kfree(&pdev->dev, msc); > + mpam_msc_destroy(msc); > mutex_unlock(&mpam_list_lock); > + > + mpam_free_garbage(); > } >=20 > static int mpam_msc_drv_probe(struct platform_device *pdev) @@ -230,6 > +703,7 @@ static int mpam_msc_drv_probe(struct platform_device *pdev) > err =3D -ENOMEM; > break; > } > + init_garbage(msc); >=20 > mutex_init(&msc->probe_lock); > mutex_init(&msc->part_sel_lock); > diff --git a/drivers/resctrl/mpam_internal.h > b/drivers/resctrl/mpam_internal.h index 07e0f240eaca..d49bb884b433 100644 > --- a/drivers/resctrl/mpam_internal.h > +++ b/drivers/resctrl/mpam_internal.h > @@ -7,10 +7,27 @@ > #include > #include > #include > +#include > #include > #include > #include > #include > +#include > + > +/* > + * Structures protected by SRCU may not be freed for a surprising > +amount of > + * time (especially if perf is running). To ensure the MPAM error > +interrupt can > + * tear down all the structures, build a list of objects that can be > +gargbage > + * collected once synchronize_srcu() has returned. > + * If pdev is non-NULL, use devm_kfree(). > + */ > +struct mpam_garbage { > + /* member of mpam_garbage */ > + struct llist_node llist; > + > + void *to_free; > + struct platform_device *pdev; > +}; >=20 > struct mpam_msc { > /* member of mpam_all_msc */ > @@ -57,6 +74,80 @@ struct mpam_msc { >=20 > void __iomem *mapped_hwpage; > size_t mapped_hwpage_sz; > + > + struct mpam_garbage garbage; > +}; > + > +struct mpam_class { > + /* mpam_components in this class */ > + struct list_head components; > + > + cpumask_t affinity; > + > + u8 level; > + enum mpam_class_types type; > + > + /* member of mpam_classes */ > + struct list_head classes_list; > + > + struct mpam_garbage garbage; > +}; > + > +struct mpam_component { > + u32 comp_id; > + > + /* mpam_vmsc in this component */ > + struct list_head vmsc; > + > + cpumask_t affinity; > + > + /* member of mpam_class:components */ > + struct list_head class_list; > + > + /* parent: */ > + struct mpam_class *class; > + > + struct mpam_garbage garbage; > }; >=20 > +struct mpam_vmsc { > + /* member of mpam_component:vmsc_list */ > + struct list_head comp_list; > + > + /* mpam_msc_ris in this vmsc */ > + struct list_head ris; > + > + /* All RIS in this vMSC are members of this MSC */ > + struct mpam_msc *msc; > + > + /* parent: */ > + struct mpam_component *comp; > + > + struct mpam_garbage garbage; > +}; > + > +struct mpam_msc_ris { > + u8 ris_idx; > + > + cpumask_t affinity; > + > + /* member of mpam_vmsc:ris */ > + struct list_head vmsc_list; > + > + /* member of mpam_msc:ris */ > + struct list_head msc_list; > + > + /* parent: */ > + struct mpam_vmsc *vmsc; > + > + struct mpam_garbage garbage; > +}; > + > +/* List of all classes - protected by srcu*/ extern struct srcu_struct > +mpam_srcu; extern struct list_head mpam_classes; > + > +int mpam_get_cpumask_from_cache_id(unsigned long cache_id, u32 > cache_level, > + cpumask_t *affinity); > + > #endif /* MPAM_INTERNAL_H */ > diff --git a/include/linux/arm_mpam.h b/include/linux/arm_mpam.h index > 0edefa6ba019..406a77be68cb 100644 > --- a/include/linux/arm_mpam.h > +++ b/include/linux/arm_mpam.h > @@ -36,11 +36,7 @@ static inline int acpi_mpam_parse_resources(struct > mpam_msc *msc, static inline int acpi_mpam_count_msc(void) { return > -EINVAL; } #endif >=20 > -static inline int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, > - enum mpam_class_types type, u8 > class_id, > - int component_id) > -{ > - return -EINVAL; > -} > +int mpam_ris_create(struct mpam_msc *msc, u8 ris_idx, > + enum mpam_class_types type, u8 class_id, int > component_id); >=20 > #endif /* __LINUX_ARM_MPAM_H */ > -- > 2.20.1