From: howtobserve1@tuta.io
To: Kyle Manna <kyle@kylemanna.com>
Cc: Tony Luck <tony.luck@intel.com>, Borislav Petkov <bp@alien8.de>,
Jason Baron <jbaron@akamai.com>,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
James Jernigan <jameswestonjernigan@gmail.com>,
James Morse <james.morse@arm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Robert Richter <rric@kernel.org>, Yi1 Lai <yi1.lai@intel.com>,
"linux-edac@vger.kernel.org" <linux-edac@vger.kernel.org>,
"linux-kernel@vger.kernel.org" <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2] EDAC/ie31200: Add two more Intel Alder Lake-S SoCs for EDAC support
Date: Mon, 11 Aug 2025 18:33:31 +0200 (CEST) [thread overview]
Message-ID: <OXOyh9y--F-9@tuta.io> (raw)
In-Reply-To: <c2f98618-4197-41c3-9a2b-2c59841dd543@app.fastmail.com>
Hi All,
Confirmation EDAC works on 8P+4E (DID 0x4668) configuration as well, using ECC DDR4 UDIMM sticks. Validated on i7 12700 and Kingston 2666MHz ECC RAM.
Raw logs:
~ > sudo dmesg | grep -i -e edac -e ecc -e ie31200 | grep -v systemd | grep edac
[ 7.834839] caller ie31200_init_one+0x1b5/0x480 [ie31200_edac] mapping multiple BARs
[ 7.839585] EDAC MC0: Giving out device to module ie31200_edac controller IE31200: DEV 0000:00:00.0 (INTERRUPT)
[ 7.843230] EDAC MC1: Giving out device to module ie31200_edac controller IE31200_1: DEV 0000:00:00.0 (INTERRUPT)
~ > grep . /sys/devices/system/edac/mc/mc*/*_count
/sys/devices/system/edac/mc/mc0/ce_count:0
/sys/devices/system/edac/mc/mc0/ce_noinfo_count:0
/sys/devices/system/edac/mc/mc0/ue_count:0
/sys/devices/system/edac/mc/mc0/ue_noinfo_count:0
/sys/devices/system/edac/mc/mc1/ce_count:0
/sys/devices/system/edac/mc/mc1/ce_noinfo_count:0
/sys/devices/system/edac/mc/mc1/ue_count:0
/sys/devices/system/edac/mc/mc1/ue_noinfo_count:0
~ > ras-mc-ctl --error-count
Label CE UE
mc#1csrow#1channel#0 0 0
mc#1csrow#0channel#0 0 0
mc#0csrow#0channel#0 0 0
mc#0csrow#1channel#0 0 0
~ > ras-mc-ctl --status
ras-mc-ctl: drivers are loaded.
~ > ras-mc-ctl --mainboard
ras-mc-ctl: mainboard: DFI Inc. model ADS310
~ > lscpu
Architecture: x86_64
CPU op-mode(s): 32-bit, 64-bit
Address sizes: 46 bits physical, 48 bits virtual
Byte Order: Little Endian
CPU(s): 20
On-line CPU(s) list: 0-19
Vendor ID: GenuineIntel
Model name: 12th Gen Intel(R) Core(TM) i7-12700
CPU family: 6
Model: 151
Thread(s) per core: 2
Core(s) per socket: 12
Socket(s): 1
Stepping: 2
CPU(s) scaling MHz: 22%
CPU max MHz: 4900.0000
CPU min MHz: 800.0000
BogoMIPS: 4225.00
Thanks
Aug 12, 2025, 00:19 by kyle@kylemanna.com:
> On Fri, Aug 1, 2025, at 23:01, Kyle Manna wrote:
>
>> Host Device IDs (DID0) correspond to:
>> * Intel Core i7-12700K
>> * Intel Core i5-12600K
>>
>> See documentation:
>> * 12th Generation Intel® Core™ Processors Datasheet
>> * Volume 1 of 2, Doc. No.: 655258, Rev.: 011
>> * https://edc.intel.com/output/DownloadPdfDocument?id=8297 (PDF)
>>
>> Signed-off-by: Kyle Manna <kyle@kylemanna.com>
>> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>> ---
>> Changes in v2:
>> - Rebased on top of a6923c06a3b2e2c534ae28c53a7531e76cc95cfa
>> - Added comments to Device ID definitions as requested
>> - Added Reviewed-by tag from Qiuxu Zhuo
>>
>> drivers/edac/ie31200_edac.c | 4 ++++
>> 1 file changed, 4 insertions(+)
>>
>
> Hi Tony, Jason,
>
> Gentle ping on this small EDAC/ie31200 change that adds two more Alder Lake-S device IDs for ECC-capable part.
>
> Reviewed-by: Qiuxu Zhuo <qiuxu.zhuo@intel.com>
>
> Could you please pick this up for the EDAC tree (ras edac-for-next)?
>
> Thanks,
> - Kyle
>
prev parent reply other threads:[~2025-08-11 16:33 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-08-02 6:01 Kyle Manna
2025-08-11 15:50 ` Kyle Manna
2025-08-11 16:33 ` howtobserve1 [this message]
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