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charset="us-ascii" Content-Transfer-Encoding: quoted-printable Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-OriginatorOrg: cadence.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-AuthSource: PH7PR07MB9538.namprd07.prod.outlook.com X-MS-Exchange-CrossTenant-Network-Message-Id: 9e2600a5-6451-4c13-ff36-08dcc27f1bf4 X-MS-Exchange-CrossTenant-originalarrivaltime: 22 Aug 2024 07:50:36.5042 (UTC) X-MS-Exchange-CrossTenant-fromentityheader: Hosted X-MS-Exchange-CrossTenant-id: d36035c5-6ce6-4662-a3dc-e762e61ae4c9 X-MS-Exchange-CrossTenant-mailboxtype: HOSTED X-MS-Exchange-CrossTenant-userprincipalname: 2fLWBfQ49bqYgqcM49TDZPV6blZOKlOUHet2mkyz9HXWJSCsD04A8LYZonOj7lz4FOxNAMY4TC680DMYT5fjPxaKn2HgxrAHEv9M1zbKnZw= X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN0PR07MB8245 X-Proofpoint-GUID: _jL-lUw18s0g-kVCIHwf1N_-H8QB5xwt X-Proofpoint-ORIG-GUID: _jL-lUw18s0g-kVCIHwf1N_-H8QB5xwt X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1039,Hydra:6.0.680,FMLib:17.12.28.16 definitions=2024-08-22_03,2024-08-19_03,2024-05-17_01 X-Proofpoint-Spam-Details: rule=outbound_check_notspam policy=outbound_check score=0 priorityscore=1501 lowpriorityscore=0 impostorscore=0 adultscore=0 mlxscore=0 spamscore=0 malwarescore=0 phishscore=0 suspectscore=0 clxscore=1015 mlxlogscore=778 bulkscore=0 classifier=spam adjust=0 reason=mlx scancount=1 engine=8.19.0-2407110000 definitions=main-2408220057 >On 24-08-21 06:07:42, Pawel Laszczak wrote: >> Stop Endpoint command on LINK TRB with TC bit set to 1 causes that >> internal cycle bit can have incorrect state after command complete. > >You mean this issue is: the transfer ring is on the LINK TRB when stop end= point >command is going to execute? Yes, but also TC bit must be set in such LINK TRB. > >What's the use case we could find this issue? I was not able to recreate this issue with standard linux and windows drive= rs.=20 To recreate this issue I used: 1. device with 2 x ACM connected to Windows OS host 2. UartAssist V5.0.10.exe=20 3. Vendor specific ACM driver Test scenario will open & close port many times during testing. Host driver should send clear feature (halt) request to device when application open the acm function port. Thanks, Pawel > >Peter > >> In consequence empty transfer ring can be incorrectly detected when EP >> is resumed. >> NOP TRB before LINK TRB avoid such scenario. Stop Endpoint command is >> then on NOP TRB and internal cycle bit is not changed and have correct >> value. >> >> Fixes: 3d82904559f4 ("usb: cdnsp: cdns3 Add main part of Cadence >> USBSSP DRD Driver") >> cc: >> Signed-off-by: Pawel Laszczak >> --- >> drivers/usb/cdns3/cdnsp-gadget.h | 3 +++ >> drivers/usb/cdns3/cdnsp-ring.c | 28 ++++++++++++++++++++++++++++ >> 2 files changed, 31 insertions(+) >> >> diff --git a/drivers/usb/cdns3/cdnsp-gadget.h >> b/drivers/usb/cdns3/cdnsp-gadget.h >> index e1b5801fdddf..9a5577a772af 100644 >> --- a/drivers/usb/cdns3/cdnsp-gadget.h >> +++ b/drivers/usb/cdns3/cdnsp-gadget.h >> @@ -811,6 +811,7 @@ struct cdnsp_stream_info { >> * generate Missed Service Error Event. >> * Set skip flag when receive a Missed Service Error Event and >> * process the missed tds on the endpoint ring. >> + * @wa1_nop_trb: hold pointer to NOP trb. >> */ >> struct cdnsp_ep { >> struct usb_ep endpoint; >> @@ -838,6 +839,8 @@ struct cdnsp_ep { >> #define EP_UNCONFIGURED BIT(7) >> >> bool skip; >> + union cdnsp_trb *wa1_nop_trb; >> + >> }; >> >> /** >> diff --git a/drivers/usb/cdns3/cdnsp-ring.c >> b/drivers/usb/cdns3/cdnsp-ring.c index 275a6a2fa671..75724e60653c >> 100644 >> --- a/drivers/usb/cdns3/cdnsp-ring.c >> +++ b/drivers/usb/cdns3/cdnsp-ring.c >> @@ -1904,6 +1904,23 @@ int cdnsp_queue_bulk_tx(struct cdnsp_device >*pdev, struct cdnsp_request *preq) >> if (ret) >> return ret; >> >> + /* >> + * workaround 1: STOP EP command on LINK TRB with TC bit set to 1 >> + * causes that internal cycle bit can have incorrect state after >> + * command complete. In consequence empty transfer ring can be >> + * incorrectly detected when EP is resumed. >> + * NOP TRB before LINK TRB avoid such scenario. STOP EP command is >> + * then on NOP TRB and internal cycle bit is not changed and have >> + * correct value. >> + */ >> + if (pep->wa1_nop_trb) { >> + field =3D le32_to_cpu(pep->wa1_nop_trb->trans_event.flags); >> + field ^=3D TRB_CYCLE; >> + >> + pep->wa1_nop_trb->trans_event.flags =3D cpu_to_le32(field); >> + pep->wa1_nop_trb =3D NULL; >> + } >> + >> /* >> * Don't give the first TRB to the hardware (by toggling the cycle bit= ) >> * until we've finished creating all the other TRBs. The ring's >> cycle @@ -1999,6 +2016,17 @@ int cdnsp_queue_bulk_tx(struct >cdnsp_device *pdev, struct cdnsp_request *preq) >> send_addr =3D addr; >> } >> >> + if (cdnsp_trb_is_link(ring->enqueue + 1)) { >> + field =3D TRB_TYPE(TRB_TR_NOOP) | TRB_IOC; >> + if (!ring->cycle_state) >> + field |=3D TRB_CYCLE; >> + >> + pep->wa1_nop_trb =3D ring->enqueue; >> + >> + cdnsp_queue_trb(pdev, ring, 0, 0x0, 0x0, >> + TRB_INTR_TARGET(0), field); >> + } >> + >> cdnsp_check_trb_math(preq, enqd_len); >> ret =3D cdnsp_giveback_first_trb(pdev, pep, preq->request.stream_id, >> start_cycle, start_trb); >> -- >> 2.43.0 >>